[gic]-gicv3/gicv4的feature總結

快速連結:

.

👉👉👉 個人部落格筆記導讀目錄(全部) 👈👈👈

GICv3.0 Key features

• Support for large systems (up to 2^32 PEs)
• Large numbers of cores on both single-chip implementations and multi-chip implementations
• New interrupt type, LPIs, which increases the number of interrupts
• LPIs also provided better alignment with PCIe, translating MSIs to interrupts by Interrupt Translation Service (ITS)
• Full MSIs support for SPIs and LPIs
• New system register interface for handling interrupts
• Optional legacy mode for backwards compatibility with GICv2

GICv3.0 implementations by Arm:

• GIC-500
• GIC-600

GICv3.1 key features

• Support for an additional 1024 SPIs
• Targeted at multi-chip implementations, where the number of SPIs per chip is low, but the number of chips means that the existing range is exhausted
• Support for an additional 64 PPIs per PE
• Support for MPAM, to align with Armv8.4
• Only specifies how software configures PARTIDs/PMGs, not what the GIC uses them for
• Based heavily on the MPAM specification
• Support for Secure virtualization, to align with Armv8.4-A
• Extends existing GICv3.0 support to Secure state

GICv3.1 implementation by Arm:

• GIC-700

GICv3.2 key features

To support Armv8-R AArch64 architecture, GICv3.2 introduced a minimal set of changes:

• Removed legacy support
• Removed SEI support in GIC CPU Interface
• Mandated support for TDIR

GICv4.0 key features

• Support for direct injection of virtual LPIs
• Reduces the number of required entries to Hypervisor, reducing overhead of virtualization

GICv4.1 key features

• Support for direct injection of virtual SGIs
• Allow more use of GICv4.0 direct injection logic, extending benefits of direct injection to vSGIs
• Improved doorbell mechanism, to increase efficiency of taking vPE from idle to schedulable

GICv4.1 implementation by Arm

• GIC-700