小數分頻N.5分頻

• 2.5分頻波形圖
• • 原理分析
  • verilog code
  • testbench
  • 仿真結果

部落客之前寫過三分頻，今天有空補充一下小數分頻，原理大同小異，具體可以參考部落客之前的部落格三分頻

2.5分頻波形圖

{signal: [

{name: ‘clkp’, wave: ‘P…’},

{name: ‘counter’, wave: ‘x2222222222’, data: [‘00001’, ‘00010’, ‘00100’, ‘01000’,‘10000’,‘00001’, ‘00010’, ‘00100’, ‘01000’,‘10000’]},

{name: ‘posedge’, wave: ‘0h.l…h.l…’},

{name: ‘clkn’, wave: ‘N…’},

{name: ‘negedge’, wave: ‘l…nhpl.nhp’},

{name: ‘D2.5’, wave: ‘lh.nhph.nhp’}

]}

原理分析

上圖是部落客分析小數分頻時所畫的時序圖，分别為1.5 以及2.5 分頻，總結就是在進行N.5分頻是shiftcount需要2N位 分别采用上升沿與下降沿進行采樣，其中采樣的高電平時間為N，最後将二者的結果進行或運算。

verilog code

module D2div5(
				input clk,
  				input reset,
  				output D2div5,
  output [4:0] count,
  output clkN,
  output clkP
			);
  reg [4:0] count;
  wire [4:0]shiftcount;
  reg clkP,clkN;
  
assign shiftcount = 5'b00001;

  always @ (posedge clk ,negedge reset)
    if(!reset)
      count <= shiftcount;
  	else
      count <= {count[3:0],count[4]};
  
  always @ (negedge clk or negedge reset)
    if(!reset)
      clkN <= 1'b0;
  else if(count == 5'b01000 || count == 5'b10000)
       clkN <= 1'b1;
  else clkN <= 1'b0;
  
  always @ (posedge clk or negedge reset)
    if(!reset)
      clkP <= 1'b0;
  else if(count == 5'b00001 || count == 5'b00010)
       clkP <= 1'b1;
  else clkP <= 1'b0;
  
assign D2div5 = clkP | clkN;
           

testbench

// Code your testbench here
// or browse Examples
module txt();
reg clk;
reg reset;
wire D2div5;
  wire [4:0] count;
   wire clkN;
  wire clkP;
initial
  begin
    $dumpfile("d.vcd");
    $dumpvars(1);
    clk = 0;
    reset =0;
    #10
    reset =1;
  end
always # 10 clk = ~clk;
  
D2div5 D2div5_inst(
				.clk,
  				.reset,
  				.D2div5,
                .count,
   .clkN,
  .clkP
			);
endmodule
endmodule

           

仿真結果