As copper's effectiveness continues to decline, chipmakers' focus on new interconnect technologies is increasing, setting the stage for a major shift in performance improvements and heat reduction in future nodes and advanced packaging.
The introduction of copper interconnects in 1997 revolutionized the standard tungsten through-hole/aluminum wire metallization scheme at the time. The Dual damascene integration schemes replace "dry" steps such as plasma etching and deposition with "wet" processes such as electroplating and CMP. At the time, manufacturers were struggling to minimize RC latency in the face of more complex interconnect structures.
Nearly three decades later, the semiconductor industry is at a similar crossroads. The shrinking line size is approaching the electron mean free path of copper. Barrier layers are consuming a larger share of the total available line width. The demand for copper alternatives is growing. However, as with most radical changes, manufacturers want to postpone this change as much as possible.
Results presented at the recent IEEE Interconnect Technology Conference show that optimization opportunities for copper remain.
The history of copper interconnects
Interconnects, the wires that carry current between transistors, are a particularly concerned area. As chips become more compact, interconnects need to take on greater tasks in smaller sizes. Before the advent of pass-wires, aluminum was the ideal material for interconnects and the industry standard at the time, but its ability to conduct electricity is rapidly approaching its limit. In addition, aluminum wires are more prone to breakage.
Copper wire coincided with its introduction.
In fact, everyone has known about the limitations of aluminum for a long time, and everyone knows that the era of aluminum is obviously numbered, but despite decades of research, no one has found a way to safely integrate copper into chip design. The main obstacle is overcoming the troubling by-products of copper-silicon interactions. Unlike aluminum, copper effectively leaks atoms and destroys the electrical properties of silicon, which can make silicon unusable. "Copper is considered the killer of semiconductor devices," said Lubomyr Romankiw, IBM Fellow and copper application expert, in the IBM Research Journal. "The conventional wisdom is to stay away from copper as much as possible."
For copper interconnects to be viable, three issues need to be addressed: determining how best to chemically deposit them on the wafer, how to protect silicon from poisoning, and how to physically place copper on the chip.
IBM has tested several methods of applying copper, including depositing solid copper from a gas suspension and using an electric charge to absorb copper ions from the liquid onto silicon, a process known as electroless plating. While the former method, known as sputtering, initially seemed promising, scientists eventually opted for the third option, electrolytic plating, which was an impractical but familiar method – and surprisingly successful.
To protect the wafers, IBM scientists used a stable metal that the company had researched in the mid-'80s as a diffusion barrier against stray copper ions. The company devised a method for depositing a diffusion barrier on a wafer along with copper. The researchers borrowed an etching technique that IBM invented for its DRAM project in the early 80s of the 20th century.
The technique is named after the paleometallurgists of Damascus, Syria, who perfected the metal inlay process, a so-called double inlay method used to etch copper interconnects and through-holes, which was critical to the success of the project. By removing the deposition and polishing steps from the typical manufacturing process, this approach creates a significant economic incentive to pursue a viable copper solution.
So, in 1997, IBM shocked the world by introducing a new semiconductor made of copper. The successful use of copper as a metal in chip manufacturing has been unattainable by scientists for more than 30 years. This breakthrough led to faster, lower-cost chips and opened up a new roadmap for the development of microprocessors. Because copper wire is more durable, 100 times more reliable, and can be scaled down to smaller sizes, the replacement of copper wire has led to an explosion of computing power in devices ranging from smartphones to automobiles.
Get the most out of copper
Nearly three decades after the interview, though, the problem came to the fore.
As the interconnect shrinks, the interface and its properties are more closely related to the electrical properties than the bulk material properties. Samsung Semiconductor's Senior Engineer Jongmin Baek and his colleagues have specialized in how to optimize the barrier and etch stop layers required for copper to improve overall performance. For example, in the Contact Metal-Spacer Test Vehicle, the team used sidewall plasma pre-treatment to reduce the thickness of the sidewall barrier by one-third, resulting in a 2% increase in contact resistance.
Samsung researchers paid particular attention to the via bottom barrier. Since the metal vias are located on metal wires, the barrier is not required as an electrical insulator or diffusion barrier. It exists only as a product of sidewall deposition, but it can account for more than 60% of the through-hole resistance. Selective deposition methods are often used to reduce through-hole bottom deposition. In Baek's work, the polymer inhibitor improved selectivity over the commonly used self-assembled monolayer, resulting in a 20% reduction in electrical resistance.
Modern interconnect schemes rely on a variety of carbon-doped oxides to achieve the "C" part of the circuit's RC delay. Materials with lower densities have a lower dielectric constant (k) and are therefore attractive. Other work by Samsung's Kang Sub Yim considers the depletion of carbon on the dielectric surface due to plasma etching. Etch damage of low-k dielectrics increases the effective dielectric constant, which increases the capacitance of the circuit. Materials with higher densities (typically with k-values above 3.0) are more resistant to plasma etching damage, which may result in lower effective k-values in sub-30nm features. For features smaller than about 30nm, the effect of surface carbon consumption is greater than the volume permittivity.
The Yim team also utilized surface siliconization to repair etch damage. However, Baek points out that surface treatment of the dielectric sidewall may contaminate the exposed metal at the bottom of the via. Instead, the Baek team employs a proprietary chemistry-based thermal recovery process that restores the etched Si-OH termination surface to a Si-CH3 termination surface.
The full encapsulation of copper wire consists of a metal cap (usually cobalt) to reduce electromigration, followed by an insulating etching stop and barrier layer. As the spacing decreases, these layers account for an increasing proportion of the total line thickness. To improve the interface with the capstone, Baek added a plasma pretreatment before etching stopped layer deposition. As a result, they found a 30% reduction in stress in the copper wire and a 10% reduction in through-hole resistance. Yim also achieved similar results.
Ruthenium through-holes, then wiring
While all these developments are promising, there is still a need for a long-term copper successor. Due to the small size and large number of vias, it is dominating the overall interconnect resistor. In the first four or five interconnect layers, the metal wires are very short and don't create much resistance. Therefore, an alternative is to use a transitional hybrid metallization scheme, where copper wire is combined with materials such as tungsten, ruthenium, or molybdenum for through-holes.
Simulations from IMEC show that the use of ruthenium vias in the first four layers of the interconnect stack can reduce the total resistance by up to 60%. To integrate ruthenium vias with copper wires, they recommend depositing only a TaN barrier layer on the dielectric sidewall, placing the ruthenium directly on the exposed copper. Any such scheme requires good dielectric surface passivation and good control of ruthenium selectivity. The cluster tooling process is preferred because removing the primary oxide from exposed copper can damage the dielectric passivation.
Because ruthenium can be deposited or etched in a variety of ways, and does not require a barrier layer, it opens the door to more flexible integration options. For example, imec R&D engineer Giulio Marti and his colleagues benchmarked three different fully self-aligning through-hole processes.
The first and most traditional process uses EUV self-aligning double patterning, which creates spacer lines that are used to define metal lines (SADP-SIM). After transferring the spacer pattern to a SiN hard mask, the ruthenium metal layer is patterned by selective RIE etching, followed by SiO2 deposition. Highly selective etching aligns the through-hole openings with the remaining SiN features, followed by CVD ruthenium deposition to fill them.
The other two options considered by Marti were based on pillar vias, where a second layer of ruthenium was deposited on top of the first layer and separated by an etching stop layer. In these schemes, pattern transfer uses two-step ruthenium etching. First, high aspect ratio etching cuts out the desired metal wire in two layers. Then, spin-coat dielectrics fill these grooves and place a hard mask on top. The hue reversal EUV patterned the hard mask to protect the desired through-hole column, while the previous etching stop layer protected the metal wire underneath. Marti found that the two-column through-hole approach increased the number of process steps, but increased the process window. In particular, this method prevents bridging between vias and adjacent lines.
Another imec R&D engineer, Chen Wu, and his colleagues proposed an alternative by using SADP spacers instead of metals to define the dielectric signature. In this SADP-SID scheme, the hardmask material is deposited between the spacer columns and then removed. While this approach adds process complexity, it means that metal features are defined directly by the mask, giving designers greater flexibility and control over feature size.
But regardless of the specific method, Wu stresses that optimizing the ruthenium etching and deposition process is critical. The tapered ruthenium profile, the base at the base of the ruthenium feature, and the incomplete removal of the TiN adhesion layer can reduce the spacing between adjacent lines, resulting in leakage.
The integration scenario is just the beginning
A successful process integration program requires careful attention to all component layers. In the case of ruthenium, the optimization process has only just begun. Jack Rogers and colleagues at TEL's Albany Technology Center investigated the effect of adhesion layer process conditions on ruthenium deposition behavior. Ruthenium films on PVD and ALD TiN have different grain orientations, different grain orientation distributions, and different resistivity. Larger and more uniform RU grains appear to reduce resistivity, at least when the grains are smaller than the overall interconnect size.
Although ruthenium interconnects require fewer auxiliary layers than copper (which is part of the focus), the reintroduction of metal etching and dielectric filling processes is bound to keep process engineers busy for years to come.