Intel? High-Level Synthesis (HLS) Compiler
Overview
Intel? High-Level Synthesis (HLS) Compiler accelerates FPGA design by enabling hardware developers to work at higher levels of abstraction using untimed C/C++. Simulation times for abstract models developed in C/C++ typically finish in seconds vs register transfer level (RTL) simulations that can take minutes or hours. Intel HLS Compiler generates production quality RTL that is device optimized for Intel FPGAs.
Features
Uses untimed ANSI C/C++ as the golden design source
Allows users to quickly explore multiple architectures through high-level directives
Simplifies tool usage by inferring design intent from high-level constraints
Supports verification of RTL by comparison with the original C/C++ source model
Generates reusable IP for system integration using Qsys
Supports inference of streaming, memory mapped or wire interfaces
Performs device specific timing driven schedule optimization and technology mapping for Intel FPGAs
Supports industry standards including ac_int datatypes and TCL