本節講述PDSP監控的配置。
QMSS PDSP：The queue manager sub system contains two or eight packed data structure processors (PDSP) and associated hardware that allow autonomous QMSS-related tasks with interrupt notification.
PDSPs are normally loaded with firmware during configuration,then programmed with firmware-specific commands. Because the interrupt distributors service pairs of PDSPs, most firmware images can be loaded on even or odd PDSPs, with restrictions usually due
to conflicts with interrupt usage. For example,using
Acc48（一種監控queue的channel類型，取值為0~47，在Nyquist中使用） on PDSP1 and PDSP5 would cause both instances to drive the same interrupts on INTD1. If Acc48 is loaded on PDSP1, it can also be loaded on PDSP3 or PDSP7.
? Descriptor accumulator firmware that monitors
programmed queues, pops descriptors found there andinterrupts the hostwith a list of descriptor addresses (this firmware comes in 16, 32, and 48 channel builds).
Descriptor Accumulation Firmware：For accumulation purposes（為了實作監控）, the firmware will read thequeue status RAM（寄存器）toobtain
status information on the programmed queues. So the host software must program theQueue N Status and Configuration Register Dregisters with the value 0x81for every queue that is to be examined
（監控）by the firmware.This will cause the status bit in the queue status RAM to be set while the queue is not empty, and clear when empty.
The 32-channel version provides 32 high channels - i.e. channels 0 to 31that are serviced once per iteration through the channels. The 16-channel firmware provides 16 channels (0...15)
that are also scanned as fast as possible (e.g.high),
yet these trigger thelow
priority interrupts. In this way, the 16- and 32-channel accumulators may be usedtogether without interrupt interference.The48-channel
version（PDSP channel0~47，用于監控queue）provides channels0 to 31 that
are high, and channels32 to 47 that are low— serviced one at a time through each iteration through channels 0 to 31. Note that any channel in any version of the firmware may be configured
to monitor 32 contiguous queues, not just the low priority channels.
PDSP監控配置代碼：
regPtr = (u32*)0x2AB8000; //為 PDSP 1 command interface (scratch ram)寄存器首位址，即配置PDSP監控的寄存器位址
/* Wait for accumulator to be free */
for(;;)
{
if( !(*regPtr & 0x0000FF00) )
{
break;
}
}
regPtr += 4;
/* Configure accumulator */
tmp = (((u32)configPtr->multiQueueMode & 0x1) << 5) | (((u32)configPtr->listCntMode& 0x1) << 4) | (((u32)configPtr->listEntrySize& 0x3) << 2) | (intModeTmp);
*regPtr-- = (tmp << 16) | (timerLoadCntTmp);
*regPtr-- = (configPtr->maxPageEntries << 16) |queue; //queue為PDSP channel監控的queue
*regPtr-- = (u32)configPtr->listAddress;
*regPtr-- = configPtr->queueEnableMask;
*regPtr = ((u32)0x8100)|
acc48Channel; //acc48Channel為監控queue的PDSP channel.(QM user guide Table 5-3,PDSP channel,CPU,event一一對應)
/* Wait for accumulator to complete given command */
if( !(*regPtr & QM_ACCUMULATOR_COMMAND_MASK) ) //0x0000FF00
{
break;
}
}
/* Get return code from accumulator hardware */
retCode = (*regPtr & 0xFF000000)>>24; //判斷配置是否已經成功
PDSP 1 command interface 寄存器的結構（首位址是0x2AB8000，共20位元組）：
下圖為對上圖總各個byte的定義：
