作者： Saint

掘金：https://juejin.im/user/5aa1f89b6fb9a028bb18966a

微網誌：https://weibo.com/5458277467/profile?topnav=1&wvr=6&is_all=1

GitHub：github.com/saint-000

CSDN: https://me.csdn.net/qq_40531974

VHDL基礎體會篇（五）

Part5:

補充介紹TestBench

【這是一個兩輸入端的與門】

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity and2_gate is
	 port(
		 in1 : in STD_LOGIC;
		 in2 : in STD_LOGIC;
		 out1 : out STD_LOGIC
	     );
end and2_gate;
architecture beh of and2_gate is
begin
out1<=in1 and in2;
end beh;
           

通過編譯後添加testbench檔案

按向導操作生成子產品的Testbench檔案，軟體自動生成相應的代碼，我們隻要在構造體中加入相應的Process，然後在Process内加入激勵信号代碼：

library ieee;
use ieee.std_logic_1164.all;
entity and2_gate_tb is
end and2_gate_tb;
architecture TB_ARCHITECTURE of and2_gate_tb is
	component and2_gate
	port(
		in1 : in STD_LOGIC;
		in2 : in STD_LOGIC;
		out1 : out STD_LOGIC );
	end component;
	signal in1 : STD_LOGIC;
	signal in2 : STD_LOGIC;
	signal out1 : STD_LOGIC;
begin
	UUT : and2_gate
		port map (
			in1 => in1,
			in2 => in2,
			out1 => out1
		);
process
begin
in1<='0'	;  
wait for 10ns;
in1<='1';
wait for 10ns;
 in1<='0'	;  
end process;

process
begin
in2<='0'	;  
wait for 20ns;
in2<='1';
wait for 20ns;
 in2<='0'	;  
end process;
end TB_ARCHITECTURE;
           

此處要注意，有wait語句不能再用敏感信号表，否則編譯器報錯，然後兩個激勵信号的編寫最後分開用兩個Process編寫。

【這是一個D觸發器】

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity dff is
	 port(
		 d : in STD_LOGIC;
		 clk : in STD_LOGIC;
		 q : out STD_LOGIC
	     );
end dff;
architecture rtl of dff is
begin
process(clk)
begin
	if clk'event and clk='1'then
		q<=d;
	end if;
end process;
end rtl;
           

相應Testbench檔案代碼：

library ieee;
use ieee.std_logic_1164.all;
entity dff_tb is
end dff_tb;
architecture TB_ARCHITECTURE of dff_tb is
component dff
	port(
		d : in STD_LOGIC;
		clk : in STD_LOGIC;
		q : out STD_LOGIC );
end component;
signal d : STD_LOGIC;
signal clk : STD_LOGIC;
signal q : STD_LOGIC;
constant clk_cycle:time:=20ns;
begin
UUT : dff
port map (
	d => d,
	clk => clk,
	q => q
	);	 

process	
begin
clk<='1';
wait for clk_cycle/2;
clk<='0';
wait for clk_cycle/2;
end process;

process
begin
d<='0';
wait for clk_cycle/3;
d<='1';
wait for clk_cycle/3;
d<='0' ;
end process;
End TB_ARCHITECTURE;