As the cornerstone of modern electronic technology, the continuous progress of the semiconductor industry has provided a steady stream of impetus for the performance improvement and cost reduction of electronic products. With the increase of chip design complexity and the improvement of system integration, the improvement of wiring density has become an inevitable trend. At the same time, with the rapid development of technologies such as the Internet of Things, cloud computing, and big data, the demand for communication and data transmission between devices has also shown explosive growth, and the increase in the demand for I/O ports has become another key factor driving the development of semiconductor technology.
Against this backdrop, traditional packaging technologies have struggled to meet the increasing performance and integration requirements. As a result, the semiconductor industry continues to explore new packaging technologies to meet the challenges of increased routing density and increased demand for I/O ports. Fan-out packaging, as an advanced packaging technology, has gradually become a new favorite in the field of semiconductor packaging with its unique advantages.
01
Features of the Fan-out package:
Smaller size: The fan-out package does not require a package board, so it can realize the need for thin packages. Through Fan-out packaging technology, different chips can be integrated into a single two-dimensional package, realizing a thin SiP (System in Package) packaging technology, which changes the original way of using straight-through silicon die via (TSV) to vertically stack multiple chips.
Stronger performance: At the same chip size, the Fan-out package can achieve a wider range of redistribution layers (RDLs) with a higher number of layers. As the number of RDL layers increases, so does the number of pins and I/O of the chip. Chips with different functions are integrated into a single package through RDL connection, which will be more powerful.
Low cost: The packaging body produced by Fan-out packaging technology can greatly shorten the complicated process and reduce the use of materials, thereby effectively reducing the production cost and realizing the advantages of low cost.
扇出型封装主要分为扇出型晶圆级封装(Fan-Out Wafer Level Packaging, FOWLP)和扇出型板级封装 (Fan-Out Panel Level Packaging, FOPLP)两种。
As an emerging technology of heterogeneous integrated packaging, fan-out packaging technology has developed to the board level, because it can be produced in a larger area to achieve the purpose of further reducing production costs and meeting the needs of the market for chip performance, and is becoming the most potential technology platform in advanced packaging technology that can provide heterogeneous integration and reduce production costs at the same time.
Let's take a look at the specific advantages of FOPLP over FOWLP, and what application fields they are suitable for.
02
FOWLP vs. FOPLP battle
FOWLP is a type of wafer-level packaging (WLP). WLP differs from traditional packaging in the order in which wafers are diced and packaged. In the traditional packaging process step, packaging is carried out after the die is diced and sliced, while wafer-level packaging is packaged first and then diced.
Let's review WLP. WLP came out around 2000 and came in two types: Fan-in and Fan-Out. In the beginning, WLP mostly adopted the Fan-in type, which can be called Fan-in WLP or FIWLP, which is mainly used in chips with a small area and a small number of pins.
With the improvement of IC technology, the chip area is reduced, and the number of pins in the chip area cannot be accommodated, so the Fan-Out WLP package form, also known as FOWLP, is derived, which realizes the full use of RDL for connection outside the chip area to obtain more pin count.
FOPLP borrows FOWLP's ideas and techniques, but with a larger panel. As a result, FOPLP offers significant productivity gains, efficiency gains, and cost reductions. Its high area utilization effectively reduces waste, and at the same time, it can process more chips in a single packaging process, which significantly improves packaging efficiency and forms a strong scale effect, so as to have a strong cost advantage.
According to the Yole report, for example, the area utilization rate of FOWLP technology < 85%, and the area utilization rate of FOPLP > 95%, which can place more chips and the cost is cheaper than FOWLP; The cost of panel-level packaging will be reduced by 66% compared to wafer-level packaging.
Source: ASE Group, Guosheng Securities Research Institute
FOPLP 拥有更高的面积利用率。 来源：STATS ChipPAC & Rudoph Technologies
In addition, FOPLP is more flexible in the choice of substrates, and can be made of glass substrates or metal substrates.
According to Yole's report, as the substrate area increases, the cost of chip manufacturing gradually decreases. Transitioning from 200mm to 300mm can result in cost savings of approximately 25%, while transitioning from 300mm to board level packaging can result in cost savings of up to 66%.
FOPLP and FOWLP each have their own subdivisions, FOWLP focuses on packaging directly on the wafer, has the characteristics of small size and high integration, and is suitable for high-performance, high-density application scenarios, such as the production of large chips such as CPU, GPU, FPGA, etc.; FOPLP, on the other hand, provides a larger package size and higher production flexibility by packaging at the panel level, enabling a wider range of packaging needs. FOPLP focuses on the application of high-power, high-current power semiconductor products, which does not require the most advanced process and equipment, nor does it require too fine line width/line spacing, and is applied to the production of APE, PMIC, power devices and other chips with about 10-500 I/O numbers.
As an important branch of the development of advanced packaging technology, FOPLP is being sought after by many manufacturers.
03
There is a shortage of CoWoS, and FOPLP has an opportunity
The most popular advanced packaging in the market is CoWoS. CoWoS can be viewed separately, CoW (Chip-on-Wafer) refers to chip stacking, and WoS (Wafer-on-Substrate) is to package stacked chips on a substrate. According to the arrangement, it is divided into 2.5D and 3D, which can not only reduce the space required by the chip, but also effectively reduce the power consumption, so as to achieve the goal of accelerating computing but the cost is still controllable.
With the advent of ChatGPT, generative AI is popular all over the world, driving strong demand for AI chips, Nvidia's (NVIDIA) H100, A100 are all manufactured by TSMC, and use TSMC's CoWoS advanced packaging technology, in addition to NVIDIA, AMD MI300 has also introduced CoWoS technology, resulting in CoWoS production capacity in short supply.
Therefore, many manufacturers have begun to look for some other solutions to solve the capacity problem, which also brings new opportunities for FOPLP packaging.
Liu Hongjun, deputy general manager of Suzhou Jingfang Semiconductor, said: Due to its process size, FOPLP technical indicators are weaker than TSMC's CoWoS-S, but its potential advantage is the possibility of breaking through cost and capacity bottlenecks. These factors have prompted current CoWoS users to strive to find alternative technologies.
As a rising star in fan-out packaging, FOPLP is attracting the attention of the whole industry with lower cost and greater flexibility. Therefore, FOPLP has also become the choice of many large manufacturers.
04
FOPLP shines in these markets
In recent years, the development of AIoT, 5G, autonomous driving and photovoltaic energy storage industries has greatly boosted the demand for power devices, sensor chips and RF chips.
According to Prismark's forecast, by 2026, 5G & Internet of Things and automotive electronics will become the only two applications that will increase market share, accounting for nearly 30% of the total semiconductor revenue; Among them, in the automotive field, with the evolution of the new four modernizations of automobiles, a traditional car used about 500-600 chips, and now the average number of chips required per vehicle has reached 1000-2000, so automotive chips will become the application category with the highest chip growth rate.
The rapid development of automotive electronics has made the importance of fan-out packaging more and more obvious. 77% of the value of semiconductors in a new energy vehicle will be produced in fan-out packages, and 66% of this can be attributed to FOPLP technology.
In addition, FOPLP relies on the sophisticated rewiring layer (RDL) process to achieve high-speed and high-density interconnection between chips (D2D), which is essential for AI computing, ensuring the seamless transmission and efficient processing of huge data streams, and directly hitting the pain points of data processing in the AI era. Furthermore, FOPLP's obvious advantages in enhancing the functional integration of chips, reducing the interconnection distance, and promoting system design innovation coincide with the high-performance and high-integration standards for chips in the AI era, laying a solid foundation for the future of intelligent computing.
Therefore, from the perspective of the application market, the future FOPLP technology is promising. The core lies in the fact that among many advanced packaging technologies, board level packaging technology is the best solution for the production of automotive-grade chips such as power devices, sensors, and communications that are growing rapidly due to their large production capacity and cost advantages.
05
Many manufacturers are popular
When it comes to FOPLP, Samsung is the absolute leader. In 2018, Samsung Electro-Mechanics achieved a new milestone with the introduction of an APE-PMIC device with fan-out embedded panel-in-package (ePLP) PoP technology for the Samsung Galaxy Watch. Samsung Electro-Mechanics continues to innovate for cost-effective, high-density fan-out packaging in order to once again compete with TSMC for Apple's packaging and front-end businesses.
Last year, Samsung's DS division's Advanced Packaging (AVP) business team began research and development of FOPLP advanced packaging technology for 2.5D chip packaging. With this technology, Samsung expects to be able to integrate the SoC and HBM into the silicon middle layer, further building it into a complete chip.
Judging from the FOPLP-related papers published by Samsung at international academic conferences, Samsung is working on the development of FOPLP advanced packaging technology to overcome the limitations of 2.5D packaging. Therefore, once Samsung successfully applies FO-PLP advanced packaging technology, it will be able to create synergies with its foundry and memory business. As a result, Samsung is attracting customers by proposing a turn-key solution, which is to attract customers by producing semiconductors for AI designers such as NVIDIA and AMD, as well as providing HBM and packaging technologies. So, if it becomes competitive in packaging, Samsung will be able to grow its semiconductor business. TSMC has exerted a huge influence in the semiconductor foundry market due to its 2.5D advanced packaging. Industry insiders said that Samsung may plan to use 2.5D advanced packaging technology to catch up with TSMC.
ASE is also one of the earliest leading manufacturers to deploy panel-level fan-out technology. The production line was completed at the end of 2019 and mass-produced in the second half of 2020, which is used in the fields of RF, FEM, Power and Server. In 2022, ASE launched the VIPack advanced packaging platform to provide vertically interconnected integrated packaging solutions. VIPack is an advanced interconnection technology solution with 3D heterogeneous integration as the key technology to establish a complete collaborative cooperation platform.
In addition, manufacturers such as PTI and Innolux have invested in the mass production of fan-out board level packaging technology based on their own process capabilities. With the increasing attention of FOPLP, in recent years, manufacturers with different business models in the industry have joined the market battle, including IDM factories, foundries, packaging factories, and even panel factories, PCB factories, etc., and they have strongly sensed the opportunity to get involved in the field of advanced packaging through fan-out technology.
Fan-out panel-level packaging manufacturers in Chinese mainland are also riding the catch, and many manufacturers have mass production or production capacity. Like what:
China Resources Micro, ESWIN, Zhongke Sihe, Tianxin Interconnection, etc. have all cut into fan-out panel-level packaging.
In 2018, CR Microelectronics established Silicon Pan Microelectronics (Chongqing) Co., Ltd. to engage in panel-level packaging business, which effectively solves the problem of high cost of chiplet packaging and is more suitable for the heterogeneous integration of power semiconductor packaging. It is reported that Sipan has a world-class team in the market, design, equipment, process and materials in the field of advanced packaging, and can provide customers with a full range of fan-out packaging technology solutions - ONEIRO packaging.
Founded in 2017 and affiliated to Beijing ESWIN Technology Group Co., Ltd., Chengdu ESWIN System Integrated Circuit Co., Ltd. has three core businesses: chips and solutions, silicon materials, and advanced packaging and testing. Chengdu ESWIN System Integrated Circuit Co., Ltd. is an advanced FOPLP (panel level fan-out) packaging and testing base in Chengdu, providing customers with cost-effective system integration packaging and testing services.
Relying on system-in-package (SiP) and board-level fan-out packaging (FOPLP) platforms, Tianxin Internet Technology Co., Ltd. provides customers with highly integrated and miniaturized semiconductor device module packaging solutions and semiconductor test interface solutions, which are widely used in high-end medical, industrial control, communications, semiconductor testing and other fields. The company has R&D teams and manufacturing plants in Shenzhen and Wuxi to provide customers with one-stop services such as scheme evaluation, design simulation, packaging and testing. The Wuxi branch of Tianxin Internet Technology Co., Ltd. is currently carrying out research on fan-out wafer-level packaging technology.
Zhongke Sihe is also committed to building a board-level power chip fan-out packaging process manufacturing platform, and on the basis of this platform, it carries out advanced Fan-out packaging process technology research and power chip/module product research, and conducts R&D, manufacturing and sales of new high-density power chips/modules for customers in various fields such as consumer electronics, industrial control, automotive electronics, communications/servers, and medical treatment, with product types covering TVS, MOSFET, SBD, Bridge, DC-DC, IPM and other devices and modules. At present, Zhongke Sihe has mass-produced DFN TVS series products based on board-level fan-out packaging. The TVS product series has been applied in batches in terminal brands such as Xiaomi, Haier, and Hisense.
06
Constraints and opportunities
At present, it should be noted that there are still many constraints faced by FOPLP in order to develop comprehensively, because it covers a variety of equipment and process difficulties in the process of process implementation, and faces multiple challenges such as precision, efficiency and speed. Among them, the failure to standardize panel size and assembly process is the biggest obstacle to the application of FOPLP. At the same time, although the size of the FOPLP package is large, the yield is not as good as that of FOWLP, so improving the yield is also the focus of its development.
In the future, with the continuous maturity and improvement of FOPLP technology, and more manufacturers in different fields to join this camp, fan-out packaging technology is expected to gradually mature and popularize.
According to YoleIntelligence's 2023 fan-out packaging market report, the FOPLP market size will expand rapidly from $41 million in 2022 and is expected to grow at a CAGR of 32.5% to $221 million in 2028.
At the same time, FOPLP's market share in the FOWLP market will also climb from 2% in 2022 to 8% in 2028.
In the near future, FOPLP will usher in a full-scale outbreak with its unique advantages.