The common scenario for using transistors is when the level value is known, so how to convert the unknown to the known when you only know the level of the input GPIO but do not know the specific level value? This section briefly describes how to design this circuit and some of the associated use cases.
1. Convert the structure
Since the specific value of the incoming level is not known, there is a certain risk of using a voltage-controlled device (MOS) for level adaptation (overvoltage or insufficient threshold), so it is recommended to use a triode to drive the triode structure to convert the unknown level to a known level. As shown in Figure 21-1, when the unknown X input is high, Q1 is turned on, Q2 is turned off, and the output output is VCC2. When the unknown X input is low, Q1 is off, Q2 is on, and the output is GND.
Figure 21-1: NPN-NPN structure diagram
Figure 21-2 shows the NPN-PNP structure, where R3 is a preset pull-up resistor, similar to a pull-up, and R3 and R2 can divide VCC1 and cooperate with X input to form a more complex logic control. When X input is high or high impedance, Q1 is on, Q2's Vbe is less than -0.7V, Q2 is on, and the output is VCC2; when X input is low, Q1 is off, Q2's Vbe=0, Q2 is off, and the output is GND.
2. Instance use
Figure 21-3 shows the control instance of the parking APA initiated by the external IO, with the addition of VCC_12V pull-up.
Figure 21-3: Example 1
Figure 21-4 shows the commonly used hot-swap level monitoring of HDMI interfaces, and the function of HDMI (19pin)/DVI (16 pin) is Hot Plug Detect (HPD), which will be used as the basis for whether the host system sends TMDS signals to HDMI/DVI. HPD is a detection signal sent from the display output to the computer host, HPD is a way to detect whether the receiver is connected, regardless of whether the receiver is powered on or not, the IO on the SOC side is generally 1.8V, so it is necessary to convert 5V to 1.8V.
Figure 21-4: Example 2
1. When the computer is connected to the display through the HDMI interface, the host computer will add +5V voltage to the DDC memory (EDID data memory) of the display through the 18th pin (PWR_CON_PIN18) of HDMI to supply power to the DDC memory, so as to ensure that even if the monitor is not turned on, the computer host can read the EDID data through the HDMI interface.
2. When the monitor detects a stable 5V voltage signal, it will pull up the HPD signal (HPD is also generated by the 5V signal of the 18 pins of the host, that is to say, the HPD signal will also be raised when the monitor is powered off).
3. When the host (graphics controller) detects that the HPD is high, it judges that the display is connected to the host through HDMI, and reads the EDID data in the display through the 15th and 16th pin DDC channels (I2C) of the HDMI interface.
4. By reading the EDID, if it detects that the working mode range of the display is suitable for the graphics card, then the TMDS signal transmission circuit in the host graphics card starts to work.
5. The requirements of the computer host for HPD signal
When the graphics card on the computer hosts detects that the HPD pin voltage of the DVI interface is greater than 2V, it is judged that the display is connected to the host through the DVI interface: when the HPD pin voltage is detected to be less than 0.8V, it is judged that the DVI connection between the monitor and the host computer has been disconnected.
6. If the EDID content changes, the HDMI specification requires the receiver/relay device to reset the HPD signal at least 100us, so that the source device can re-read the EDID information. (This should be noted in the handling)
3. Simulation effect
Figure 21-5 shows the Spice simulation of the NPN-PNP structure, and Figures 21-6 to 21-8 show the simulation result waveform, switching the level of V2 and the output level high to V3.
Figure 21-5: Simulation legend
Figure 21-7: V2 = 1.8V
Figure 21-6: V2 = 3.3V
Figure 21-8: V2 = 10V