Advances in semiconductor technology are approaching their limits, and the pace of continuation of Moore's Law is slowing. In order to break through the limitation of the number of I/O pinouts in traditional packaging technology, fan-out wafer-level packaging adopts the method of wafer reconstruction, and uses multi-layer rewiring (RDL) and other technologies to reduce the pin spacing, reduce the packaging thickness, reduce the high-frequency signal transmission loss, and further improve the integration of the chip. In recent years, this advanced packaging technology has developed rapidly in the fields of consumer electronics and high-performance computing, and has gradually become a representative technology. However, due to the precision structure and complex process of fan-out wafer-level packaging (FOWLP), the reliability problems are becoming more and more obvious, involving a series of problems such as wafer warpage, bump cracking, and chip offset.
01
扇出型封装(FOWLP/FOPLP)
As the advanced nano process has approached the physical limit, under the influence of the contradiction between the growing performance demand and the gradual failure of Moore's Law, Intel, NVIDIA, TSMC, AMD and other established semiconductor companies have increased their investment in advanced packaging fields such as stacked packaging (PoP), FOWLP, and through-silicon via (TSV), and they should use advanced packaging technology to achieve products with higher performance, lower power consumption, smaller size, and faster signal transmission speed.
As one of the important achievements of advanced packaging technology, FOWLP has achieved great success in mobile devices and wearables, and has begun to be applied in high-performance computing, autonomous driving, and the Internet of Things. FOWLP has the potential to combine multiple packaging technologies, enabling heterogeneous integration and 3D stacking, laying the foundation for the development of future packaging technologies. FOWLP technology has been adopted in several commercial products, including key components such as FPGAs, CPUs, and DSPs, which enable them to achieve higher density, performance, and reliability.
Traditional packaging technologies, such as flip packaging and wire bonding, typically employ complex interconnect structures such as leads, vias, and solder balls to interconnect signals. However, these complex interconnect structures can affect the performance of the chip's signal transmission. In fan-out packaging, according to the process sequence of rewiring, it can be divided into two processes: chip first and chip last. According to the way the chip is placed, it can be divided into two processes: face up and face down. Based on the above classifications, packaging fabs have formed three main combination processes based on the ease of operation, namely Chip first-face up, Chip first-face down, and Chip last-face down.
In advanced die processing processes, face-up die processing is less expensive due to the need to reduce the size of the molding layer using chemical mechanical polishing (CMP) technology, which is generally less commonly used by packaging fabs. Conversely, face-down chip handling is prone to warpage when removing the carrier board and adding a rewiring layer (RDL) process, so precautions need to be taken in the process operation. RDL technology is first used in the face-down chip processing process, which can reduce the failure rate in the chip packaging process, and is currently widely used in packaging plants.
In the fan-out wafer-level packaging (FOWLP) process, the rewiring layer is one of the key steps. It forms a corresponding metal wiring pattern by depositing metal layers and insulating layers on the surface of the wafer, and uses polymer thin film materials and aluminum/copper metallization wiring to rearrange the I/O pads of the chip into a pattern distribution form, and extends them to a looser area for planting solder balls. There are two main RDL processes in fan-out wafer-level packaging, which are:
- Polymer + electroplating copper + etching
- PECVD+Cu-damascene+CMP
02
Reliability challenges and considerations
Advances in semiconductor technology are approaching their limits, and the pace of continuation of Moore's Law is slowing. In order to break through the limitation of the number of I/O pinouts in traditional packaging technology, fan-out wafer-level packaging adopts the method of wafer reconstruction. This technology utilizes technologies such as multi-layer rewiring (RDL) to reduce pin spacing, reduce package thickness, reduce high-frequency signal transmission losses, and further improve chip integration. In recent years, this advanced packaging technology has developed rapidly in the fields of consumer electronics and high-performance computing, and has gradually become a representative technology. However, fan-out wafer-level packaging (FOWLP) is becoming increasingly problematic due to its sophisticated structure and complex production process.
As the advanced nano process has approached the physical limit, under the influence of the contradiction between the growing performance demand and the gradual failure of Moore's Law, Intel, NVIDIA, TSMC, AMD and other established semiconductor companies have increased their investment in advanced packaging fields such as stacked packaging (PoP), FOWLP, and through-silicon via (TSV), to achieve products with higher performance, lower power consumption, smaller size, and faster signal transmission speed with the help of advanced packaging technology.
There are two important concepts in FOWLP: fan-out packaging and wafer-level packaging. Traditional fan-in packages place the I/O interface under the wafer, limiting the number of I/Os due to the size of the chip. Fan-out packages utilize rewiring technology and molding compounds to provide additional chip area outside the wafer, increasing the number of I/O interfaces and meeting the growing throughput needs of the chip. Wafer-level packaging is to package the entire wafer first, and then cut it, which is more suitable for mass production of large-scale integrated circuits.
With the advancement of integrated circuit packaging technology, the packaging structure has become more complex, and the number of wiring densities and I/O interfaces has increased. This complexity has led to an increase in reliability issues, especially in the FOWLP process. The FOWLP process consists of multiple steps, such as wafer reconstruction, molding, and rerouting, each of which has a significant impact on the reliability of the package.
Wafer reconfiguration is the process of reassembling chips separated from a wafer onto a temporary carrier to form a new "reconstructed wafer", as shown in the figure below. Wafer reconfiguration technology requires good positioning accuracy, both good adhesive strength and easy peeling, otherwise it will cause the chip to shift.
The epoxy molding process protects the chip and expands its surface area. However, epoxy molding compounds liquefy when exposed to heat. A mismatch in the coefficient of thermal expansion can cause wafer warpage and chip shift, while liquid flow during injection molding can also change die position. The key to achieving the fan-out effect is the rerouting technology, which first covers the surface of the grain with a passivation layer and a PI layer, then creates a metal layer pattern by metal sputtering and mask exposure, fills the metal layer using electroplating, and alternates the metal layer and polyimide layer on the surface of the die and molding material, and finally forms multiple rerouting layers to rearrange the I/O interfaces. However, due to the different coefficients of thermal expansion of metals and polyimides, the rewiring layer may crack when the temperature changes if it is not strong enough.
Common failure modes in FOWLP applications include rerouting layer delamination and solder ball cracking. The daisy-chain test link can monitor and locate FOWLP failures in real time, which is helpful for the analysis of subsequent failed package structures. Temperature cycling tests and impact tests are effective in exposing potential failure problems.
After the failure is found, the failure point can be located and analyzed by using tools and methods such as ultrasonic scanning electron microscopy (SAM), scanning electron microscopy (SEM), energy dispersive X-ray spectroscopy (EDX), and X-ray energy dispersive spectroscopy (EDS). Ultrasonic scanning electron microscopy and energy dispersive X-ray spectroscopy can pinpoint the location of failure, and scanning electron microscopy provides clear images to help understand the cause of failure. Spectroscopy can analyze the composition of materials near the failure point to help trace the cause of failure, such as insufficient purity of raw materials, incomplete cleaning, or unclean production environment.
Temperature cycling tests and impact tests expose the risk of layer delamination and solder ball cracking. In temperature cycling tests, the metal and polyimide layers of the rewiring layer are stressed due to different coefficients of thermal expansion, which can lead to cracking. Impact and temperature cycling can also lead to a concentration of thermal and mechanical stress at the solder ball, which can lead to cracking due to improper product design or packaging process. According to the standard JESD22-A104 issued by JEDEC, the temperature cycle test range is -40~125°C, the number of cycles is 1000 times, and the strength of the impact test is 1500g/ms. In practice, reliability environmental testing will be adjusted according to the product life cycle stage and application scenarios, such as aerospace products may be strengthened impact testing, automotive electronics may expand the temperature cycling range or increase high-temperature storage experiments, etc.
03
Major process defects and failure modes
Wafer warpage
Wafer warpage is macroscopic deformation of the wafer due to the accumulation of thermomechanical stress during processing. This distortion affects the process accuracy of subsequent mask lithography and limits the increase in the density of the rewiring layer. Wafer warping can cause stress to concentrate at the interposer or solder joints, which can lead to problems such as solder ball cracking and detaching and interposer delamination. The larger the wafer size, the stronger the thermomechanical stress and the more severe the warpage. With the increasing application of large-size chips in wafer-level packaging, wafer warpage has become an important challenge restricting the development of FOWLP.
Because wafer surfaces are prone to scratching, the industry often uses optical methods to measure its warpage. These methods are mainly divided into two categories: optical interferometry and laser scanning measurement. Optical interferometry, including shadow moire, projectional moire, and Temman-Greene interferometry, describes the curvature of a wafer through grating interferometric images. Laser scanning measurement uses a laser to comprehensively scan and locate the wafer, and finally fits the wafer warpage through the computer.
Wafer warpage is primarily thought to be caused by volume shrinkage caused by curing of epoxy molding compounds and mismatches with the coefficient of thermal expansion of different materials. However, with the deepening of research, especially by analyzing the deviation between traditional theoretical models and actual results, more factors affecting wafer warpage have been discovered in recent years. For example, the anisotropy of silicon and the viscoelastic relaxation effect of epoxy molding compounds also play a role in warpage.
Chip offset
Chip shift is when the wafer deviates from its proper position. This phenomenon can be observed with high-magnification microscopy and may be caused by insufficient wafer reconstruction accuracy or stress generated by subsequent process steps. There are two main types of stresses that induce chip offset. One is the fluid-induced resistance generated by the flow of epoxy molding compound during the curing process. The other is thermal expansion/contraction during the encapsulation process, curing and shrinkage of epoxy molding compounds, and thermomechanical stress caused by wafer warpage. Grain shift is most severe at the edge of the wafer, and the analysis shows that the stress due to thermomechanical effects and fluid-induced drag has a similar mechanism of action, i.e., the closer to the edge, the greater the stress. In the process of wafer reconstruction, the lack of adhesion of the temporary carrier is the most direct cause of the chip shift problem. Compared to wafer warpage, there are fewer types of stress that cause chip drift and the failure mechanism is more defined.
Cracking of solder joints
As the number of I/O interfaces in FOWLP continues to increase, the size and density of solder joints are increasing. As the size of the solder joint decreases, the stress on the individual solder joints increases, so the reliability of the solder joint becomes more and more significant.
Rerouting layers are layered
The most commonly used organic materials in the rewiring layer include polyimide (PI), polybenzoxazole (PBO) and benzocyclobutene (BCB), as well as phenolic resins. Although PI is currently the most widely used material in the rewiring layer, it has a high curing temperature, typically over 300°C. Even the modified low-temperature curing PI has a curing temperature of more than 200°C, so the process needs to be optimized. The delamination phenomenon of rewiring layers usually occurs after temperature cycling tests, and cracks appear due to the fatigue stress at the interface between the materials due to the repeated thermal expansion and contraction of different material layers. In addition, delamination of rewiring layers may also be observed in impact tests. Although rerouting layer layering is a common failure mode in fan-out packages, due to the complexity of its structure and materials, as well as its individual characteristics, the simulation of rerouting layers is difficult and requires separate analysis for different package structures.
04
Process Improvement and Reliability Optimization Design
Through experiments and simulations, the process can be quickly iterated to optimize process parameters and improve product yield. Optimizing the package structure based on mature failure physical models is an effective way to improve product reliability.
Wafers undergo drastic changes in curvature, shape, and direction during the manufacturing process, with maximum warpage occurring not at the end of the process, but at the reflow stage. Therefore, for high-density process operations, warpage at each process step should be continuously monitored and effectively controlled, rather than just end-of-line monitoring.
Liquid flow and thermomechanical effects are the two major factors that contribute to chip shift. By reducing the molding process speed and mold curing temperature, reducing the grain spacing and grain thickness, and increasing the thickness of the epoxy molding compound, the resistance caused by liquid flow can be reduced, thereby reducing die drift. On the other hand, chip shifts caused by thermomechanical effects can be reduced by reducing the thickness of the epoxy molding compound, using a temporary carrier with a low coefficient of thermal expansion, and increasing the spacing and thickness of the grains. However, there is a conflict between these measures, so there is a trade-off between process parameters. Repeated modeling and experimentation for different package structures can minimize chip offset.
One of the main reasons for the delamination of the rewiring layer is the lack of cleanliness of the production environment or the incomplete cleaning of residues from the previous process. In order to solve this problem, it is necessary to strictly monitor the production environment, use energy spectroscopy technology to detect delamination of packaged devices in a timely manner, find out the organic compounds that cause delamination, trace the source, and rectify them in a timely manner. In addition, in the rewiring process, the selection of organic materials with a high coefficient of thermal expansion that matches the metal layer and the viscosity of the demarcation layer is also the key to reducing delamination.
05
epilogue
FOWLP has been widely used in consumer and industrial semiconductor manufacturing, and has initially succeeded in the field of high-reliability chips, becoming a key technology for future business competition. A large number of FOWLP reliability physical models have been established in academia and industry, and a series of process improvements and reliability design optimizations have been carried out. However, the increasing complexity of the package structure and the coupling relationship of multiple stresses make it difficult to rely on the failure mechanism research alone to guide the deepening process and design improvement. Through machine learning and deep learning, establishing the mathematical relationship and model between process and design parameters and product yield and reliability parameters may be an effective way to guide process and design improvement and further improve product reliability, and it is also an important direction for future development.