Fundamentals of semiconductors

The basic properties of semiconductors are the key to understanding their important role in modern technology, and their unique properties make semiconductors have a wide range of applications in electronic devices. Before diving into the intricacies of semiconductor manufacturing, it is first necessary to have a solid understanding of the basic properties of semiconductors.

Explain the whole process of chip manufacturing in detail

Semiconductors refer to materials whose electrical conductivity is between that of conductors (such as metals) and insulators (such as ceramics), and this unique property allows them to control electric current, making them the basis of modern electronic devices.

1.1 Electrical properties

The conductivity of semiconductors can be altered by the process of introducing impurities, known as doping. The energy gap (or band gap) of a semiconductor is usually between 2~3 electron volts (eV), which is crucial in determining its electrical properties. It is this bandgap that distinguishes semiconductors from conductors and insulators, allowing them to conduct electricity under specific conditions.

1.2 Types of Semiconductors

Intrinsic semiconductors: Pure semiconductor materials without significant impurities, silicon and germanium are common examples
Impurity semiconductors: Semiconductors that intentionally introduce impurities through doping to alter their electrical properties

1.3 Common Materials

Elemental semiconductors

Silicon (Si): The most commonly used semiconductor material, widely used in integrated circuits, solar cells, and various electronic devices
Germanium (Ge): An early semiconductor material, mainly used in high-frequency electronics and infrared detectors

Compound semiconductors

Gallium arsenide (GaAs): High electron mobility and high-frequency characteristics, it is widely used in microwave and high-frequency electronic devices, such as mobile phones and satellite communications
Gallium nitride (GaN): With a high breakdown electric field and high electron mobility, it is commonly used in high-power and high-frequency applications such as LEDs and power electronics
Silicon carbide (SiC): With high thermal conductivity and high breakdown electric field, it is suitable for high-temperature, high-voltage electronic devices such as power electronics and automotive electronics
Indium phosphide (InP): Widely used in optical communications to make photodetectors and lasers

Emerging semiconductor materials

Two-dimensional materials (e.g., graphene): have excellent electronic and optical properties and have the potential to be used in next-generation electronics and sensors

Organic semiconductors: used in flexible electronics, displays, solar cells and other fields

other

Zinc sulfide (ZnS), zinc oxide (ZnO): used in optoelectronics and sensors

1.4 Doping process

Doping refers to the introduction of specific impurities into a semiconductor material to improve its electrical conductivity. The type and concentration of doping determine the behavior of semiconductors:

N-type doping: Atoms with more electrons are added, providing additional free electrons for conduction
P-type doping: Atoms with fewer electrons are added, forming "holes" that act as positively charged carriers

Semiconductor manufacturing process

The semiconductor manufacturing process is a complex and highly specialized series of steps that transform raw materials into functional electronic components. This process involves a variety of techniques and processes, each of which requires precise control and meticulous attention. In this section, we will provide an overview of the various stages of semiconductor manufacturing, from the growth of semiconductor crystals to the final packaging of the device.

2.1 Crystal growth

The manufacturing process begins with the growth of high-quality semiconductor crystals, which are the building blocks for the production of electronic devices. For silicon-based devices, the most common crystal growth method is the Zochralski method, which melts high-purity silicon in a crucible, then cools it to near the freezing point, pulls a single crystal from the melt by rotating the seed crystal, and slices it into thin wafers. This method allows the production of single ingots with uniform crystal structures and excellent electrical properties. Other widely used methods include the Kyropoulos method, the Float Zone method, the Verneuil method, the Bridgman method, and others. In addition, the wafers are polished and cleaned to create a clean surface for subsequent processing steps.

The main challenges in the crystal growth process include controlling the purity and temperature stability of the growth environment to avoid the introduction of impurities and defects; Adjust solution or melt saturation to ensure uniform growth rates and prevent interface roughening and the formation of irregular topography; and high-repeatability and high-quality crystal production in large-scale production. These factors affect crystal structural integrity and physical properties, making crystal growth a complex and delicate process.

2.2 Wafer preparation

Wafer preparation is a critical initial step in the semiconductor manufacturing process, as it lays the foundation for the manufacture of high-quality electronic devices. This process involves converting semiconductor crystals, such as silicon or gallium arsenide, into thin, flat wafers with extremely smooth surfaces.

The process of ingot dicing wafers is a crucial part of the semiconductor manufacturing process, which directly affects the quality and yield of the final wafer.

2.2.1 Preparation

The ingots need to be thoroughly cleaned before cutting to remove surface impurities and contaminants. Wax or other fixatives are often used to hold the ingots to the holder to ensure stability during the cutting process.

2.2.2 Cutting phase

Wafers are usually cut using a diamond wire saw or an internal circular saw. Diamond wire saws use wire coated with diamond particles, while internal circular saws are thin slices with diamond plated on the inner circle. Set parameters such as cutting speed, line tension, and cutting fluid flow. These parameters have a great impact on the cut quality and need to be optimized for the material and size of the ingot
Cutting process

Diamond wire saw cutting: The diamond wire rotates at high speed and cuts the ingots in a reciprocating motion under the cooling and lubrication of the cutting fluid. Cutting fluids are usually water-based or oil-based, and are used to cool and carry away cutting-generated debris
Internal circular saw cutting: Internal circular saw cutting principle is similar to wire saw, but it cuts ingots by rotating internal circular lamella. The dicing accuracy and speed are relatively high, which is suitable for the dicing of high-quality wafers

2.2.3 Post-cutting processing

Removal of fixative: Once the cut is complete, the wax or fixative used for ingot fixation needs to be removed. It is usually removed by heating and melting or solvent dissolution
Wafer cleaning: Wafer dicing will have residual dicing fluid and debris on the surface, which needs to be thoroughly cleaned by ultrasonic cleaning and other methods
Inspection and classification: Inspect the wafer after cutting, including parameters such as thickness, flatness, surface defects, etc. According to the test results, the qualified wafers are classified to the next process, and the unqualified wafers are reworked or discarded.

2.2.4 Polishing and etching (as required)

Preliminary polishing: In order to obtain a flat and smooth surface, some wafers are subjected to preliminary polishing after cutting
Chemical Mechanical Polishing (CMP): High-precision wafers also require CMP to further improve surface quality and flatness
Edge etching: Some processes require the edge of the wafer to be etched to prevent edge chipping and improve the mechanical strength of the wafer

Among them, there are many kinds of wire saws, including manual or automatic, supporting single or multi-wire cutting, one-way or two-way cutting, and installed on different sizes of hubs with different spindle rotation speeds. With proper tool selection and parameter optimization, wafer cutters can ensure that the wafer geometry is suitable for further processing.

During wafer preparation, the main challenges include precision control and material loss. High-precision cutting requires a stable and uniform feed of the cutter to avoid microcracks and defects. In addition, the balance of cutting speed and tool wear is critical, as too fast or too slow can affect the quality of the slices. At the same time, material loss and edge chipping during the slicing process can lead to wasted resources and increased costs, which need to be minimized by optimizing the process. Temperature control and vibration are also potential issues that can affect the smoothness and overall quality of the cut.

2.3 Lithography and Patterning

Photolithography is a crucial optical process in the manufacturing process to create complex circuit patterns on the surface of a single wafer. This is achieved by coating the wafer with a light-sensitive material, called a photoresist, and then exposing it to deep ultraviolet (DUV) or extreme ultraviolet (EUV) through a mask containing the desired pattern. The exposed photoresist undergoes a chemical change that allows it to be selectively removed. It leaves behind a graphic layer that serves as a protective layer for subsequent processing steps such as etching and deposition.

EUV Extreme Ultraviolet (EUV) lithography is a next-generation lithography technology that uses extreme ultraviolet light at a wavelength of 13.5nm. Due to its lithography accuracy of several nanometers, EUV lithography requires an extremely strict concentration of the beam, which is equivalent to a spot shining on the moon with a flashlight no more than the size of a coin. The length of the mirror used for reflection is 30cm, and the surface undulation must not exceed 0.3nm, which is equivalent to the undulation of the railway track from Beijing to Shanghai not exceeding 1mm. Each EUV lithography machine weighs 180 tons, consists of more than 100,000 parts, requires 40 containers for transportation, and takes more than a year to install and commission.

Lithography is a crucial step in the semiconductor manufacturing process because of its ability to create complex circuit patterns on the surface of wafers. These patterns form the basis of various components and structures in semiconductor devices.

2.3.1 Photoresist coating

Before the photolithography process begins, a thin layer of photosensitive material, called a photoresist, must be applied to the wafer. Photoresists are typically coated using a spin coating process, in which a small amount of photoresist is deposited onto the surface of the wafer while it is rotating at high speeds. Centrifugal force ensures that the photoresist is evenly diffused, resulting in a homogeneous coating. The basic function of a photoresist coating is to lose resistance and create a pattern through a chemical process.

There are two main types of photoresists: positive and negative. Positive photoresists become more soluble after exposure, while negative photoresists become more difficult to dissolve after exposure. The choice of photoresist depends on the specific requirements of the semiconductor device being manufactured.

2.3.2 Mask alignment

After the photoresist is applied, a photomask is used to transfer the desired pattern to the wafer. A photomask is a sheet of glass or quartz with a patterned layer of opaque material, such as chrome, that is used to block the passage of light. Use a special tool, called a mask aligner or stepper, to carefully align the wafer and photomask to ensure that the pattern is accurately positioned on the wafer surface.

2.3.3 Exposure

After the photomask is placed, the wafer is exposed to UV light, which passes through the transparent area of the photomask and hits the photoresist. Ultraviolet light initiates a chemical reaction in the exposed area of the photoresist, changing its solubility. For positive photoresists, the exposed area becomes more soluble; In the case of negative photoresists, it becomes more difficult to dissolve.

The exposure process can be carried out using various light sources, such as mercury vapor lamps or excimer lasers. With techniques such as immersion lithography, it can be further optimized to immerse wafers and photomasks in a liquid medium to improve the resolution of pattern transfer.

2.3.4 Development

After exposure, the wafer is immersed in a developer that selectively removes dissolvable areas of the photoresist to reveal the underlying pattern layer. For positive photoresists, the exposed area is removed; For negative photoresists, the unexposed area is removed. The wafer is then rinsed and dried, leaving behind a precise layer of photoresist pattern that serves as a template for subsequent manufacturing steps such as etching or deposition.

This is necessary for the production of advanced semiconductor devices.

2.4 Etching and deposition

Etching and deposition are two processes that are indispensable in the manufacturing of semiconductor devices. Etching selectively removes material from wafers through a wet chemical process or plasma process, creating complex three-dimensional structures such as transistors and interconnects. Deposition is the process of adding a thin layer of material to the surface of a wafer. Deposition techniques include chemical vapor deposition (CVD) and physical vapor deposition (PVD), which can be used to deposit a variety of materials, including metals, insulators, and semiconductors.

2.4.1 Etching

This is an essential step in the semiconductor manufacturing process, and it involves selectively removing material from the wafer to create the desired structure and features. This process is used to define the shape of various components, such as transistors, capacitors, and back-end interconnects, by removing unmasked wafer areas. In this section, we discuss key considerations for etching, including wet etching, dry etching, and etch selectivity and uniformity.

Dry etching dominates semiconductor etching, accounting for 95% of the market. The main advantage is the ability to achieve anisotropic etching, i.e. only the vertical material is removed during the etching, while the transverse material is not affected, thus guaranteeing the fidelity of the fine figures. In contrast, wet etching is difficult to control the etching direction, which can easily lead to the reduction of line width and even damage the circuit in advanced processes, thereby reducing the chip quality.

Currently, multiple template processes are widely used in semiconductor manufacturing, i.e., multiple deposition and etching processes are used to achieve the desired feature size. For example, the 14nm process requires 64 etching processes, which is 60% more than the 28nm process. The 7nm process requires up to 140 etching steps, which is 118% more than the 14nm process.

a. Wet etching

Wet etching is a chemical process in which a wafer is immersed in a liquid etchant solution, which reacts with the exposed material, dissolves it, and removes it. The choice of etching agent depends on the material being etched and the desired etching rate and selectivity. Wet etching is typically isotropic, i.e., the material is removed uniformly in all directions, which can lead to undercutting of features and limit the resolution of etched structures.

b. Dry etching

Dry etching is a gas-phase process that uses the physical action of plasma hitting the surface of a wafer, or the chemical reaction between the plasma and atoms on the surface of the wafer, or a combination of both, to remove material from the surface of a wafer. There are several types of dry etching techniques, including:

Reactive Ion Etching (RIE): Reactive ion etching combines chemical reactions and ion bombardment to etch materials. The wafer is placed in a vacuum chamber and exposed to a plasma produced by a mixture of reactive gases. The reactive species in the plasma react with the exposed material, while the ions accelerate towards the wafer and physically remove the reaction products.

Deep Reactive Ion Etching (DRIE) :D RIE is a variant of RIE that specializes in silicon etching with high aspect ratios. It utilizes alternating deposition and etching steps to achieve deep vertical trenches with smooth sidewalls.

Atomic Layer Etch (ALE): ALE is an advanced etching technology that is capable of removing one atomic layer at a time. Achieved through sequential, self-limiting reactions, this provides superior control over etch depth and profile.

c. Etching selectivity and uniformity

Etch-selectivity refers to the ability of the etching process to remove one material without affecting the other. High etch selectivity is important to protect the integrity of the wafer mask area and prevent damage to the underlying layer. Etch uniformity refers to the uniformity of the etch process across the wafer surface, which is important to ensure consistent device performance.

In summary, etch is a fundamental step in the semiconductor manufacturing process, creating complex structures and features on the surface of wafers. By carefully selecting the appropriate etch technology and maintaining high etch selectivity and uniformity, manufacturers can produce advanced semiconductor devices with high performance and reliability.

2.4.2 Thin film deposition

This process is a critical step in the semiconductor manufacturing process and is used to form a thin, uniform layer of material on the surface of the wafer. These films can be used as insulating, conductive, or doping layers to achieve the functionality of semiconductor devices. Thin film deposition processes are mainly divided into two categories: physical vapor deposition (PVD) and chemical vapor deposition (CVD). Chemical vapor deposition (CVD) is a deposition technique in which reactants are formed into a stable solid film on the surface of a wafer by means of chemical reactions such as heat, electrical discharge, or ultraviolet light. CVD technology is widely used in chip manufacturing processes to deposit dielectric, conductive, or semiconductor materials. Unlike CVD, physical vapor deposition (PVD) is a physical process that typically uses gases such as argon. In a vacuum, argon ions are accelerated against the target, causing the target atoms to be sputtered out and deposited on the wafer surface in the form of snow flakes.

a. 物理气相沉积（PVD）

PVD technology physically transfers materials from a solid or liquid source to the surface of a substrate. Common PVD methods include:

i. 蒸发沉积（Evaporation Deposition）：

The material is heated to evaporation or sublimation, forming vapors that condense on the surface of the substrate to form a thin film.
Resistance heating, electron beam heating, and laser heating.

ii. 溅射沉积（Sputtering Deposition）：

The target is bombarded with plasma and its atoms or molecules are sputtered onto the surface of the substrate.
A variety of materials including metals, oxides, and nitrides can be deposited.

b. 化学气相沉积（CVD）

The CVD process uses a chemical reaction to form a thin film on the surface of the substrate. Usually at high temperatures, the reaction gases undergo a chemical reaction on the surface of the substrate to form a solid film. Common CVD methods include:

i. Low Pressure Chemical Vapor Deposition (LPCVD):

Performed in a low-pressure environment, it helps to improve the uniformity and coverage of the film.
It is suitable for depositing silicon oxide, silicon nitride and other materials.
ii. 等离子增强化学气相沉积（PECVD）：
Plasma is used to excite and accelerate chemical reactions, allowing deposition to take place at lower temperatures.
It is commonly used to deposit silicides, nitrides, and organic films.
iii. 大气压化学气相沉积（APCVD）：
Carried out at atmospheric pressure, the process is simple but the film uniformity is low.
Ideal for large-scale applications that require lower costs.

c. Other thin film deposition technologies

In addition to PVD and CVD, there are specific thin film deposition techniques:

Molecular Beam Epitaxy (MBE):
Ultra-thin and high-quality crystalline films are formed by depositing atomic or molecular beams directly onto the substrate under high vacuum. It is suitable for high-precision and high-quality epitaxial growth.
Atomic Layer Deposition (ALD):
By alternating exposure of the substrate to different reaction gases, precise control at the atomic level is achieved. Suitable for films that require very precise thickness control.
旋涂（Spin Coating）：
The liquid material is evenly distributed on the substrate using high-speed rotation and then heat treated to form a thin film. It is commonly used in the manufacture of photoresist layers and certain organic films
Electrochemical Deposition (ECD):
ECD, also known as electroplating, is primarily used for the deposition of copper interconnects. It involves the reduction of metal ions in solution to the surface of the wafer by applying an electric current.

2.4.3 Summary

Different thin film deposition processes have their own advantages and disadvantages and application scenarios. PVD and CVD are the two most commonly used categories, but other technologies such as MBE and ALD also play an important role in specific applications.

2.5 Chemical mechanical polishing

After deposition, the wafer goes through a series of polishing steps to create a smooth, mirror-like surface. This is important because any surface defects or contaminants can adversely affect the performance and reliability of the final semiconductor device. The polishing process often combines chemical and mechanical techniques, such as chemical-mechanical planarization (CMP). The process uses a slurry containing abrasive particles and chemical reactants to remove material from the wafer surface in a controlled manner.

2.5.1 The purpose of the CMP process

The main purpose is to achieve the global flattening of the wafer surface and provide a flat substrate for subsequent lithography and etching processes. This is especially important for multi-layer interconnect structures and fine linewidth technologies. CMP is widely used in the following areas:

Planarized oxide layer (e.g. silicon oxide)
Planarized metal layers (e.g. copper, aluminum)
Planarized polysilicon layer

2.5.2 Basic principles of the CMP process

CMP combines both chemical etching and mechanical grinding technologies, and its principles can be summarized as follows:

Chemical reaction: The chemical components in the polishing slurry react with the material to be polished, resulting in compounds that can be easily removed or softening the surface of the material
Mechanical grinding: The abrasive particles in the polishing pad and polishing slurry are used to mechanically grind the material to remove the compounds and material surfaces generated by the reaction

2.5.3 Components of the CMP process

Slurry: Contains oxidants, complexing agents, corrosion inhibitors, pH adjusters, and abrasive grains, which play an important role in both chemical and mechanical aspects
Polishing Pad: Mounted on a rotating polishing pad, it has a certain hardness and elasticity, which can effectively cooperate with the polishing slurry for material removal
Polishing Machine: Includes a rotating disc, wafer fixture, and polishing slurry dispensing system. The polisher controls the pressure, speed, and time of polishing

2.5.4 CMP process steps

Wafer loading: The wafer to be polished is fixed on the wafer fixture of the polishing machine
Polishing slurry distribution: The polishing slurry is evenly distributed between the wafer and the polishing pad
Polishing: Polishing is carried out by applying the appropriate pressure and rotation speed by the polishing machine. The chemical composition softens the surface of the material, and the mechanical abrasive particles remove the softened material
Cleaning: After polishing, the wafer needs to be cleaned to remove residual polishing slurry and abrasive particles
Inspection: Use an optical microscope or other inspection equipment to check the polishing effect to ensure that the surface flatness and material removal meet the requirements

2.5.5 Key Parameters and Controls

Key parameters in the CMP process need to be precisely controlled to ensure polishing results and process stability:

Polishing pressure: Wafer breakage may result from too high pressure, and low pressure will result in low polishing efficiency
Rotation speed: includes the rotation speed of the polishing disc and wafer, which affects the uniformity and rate of polishing
Polishing slurry formulation: chemical composition, abrasive concentration, and pH value directly affect the chemical reaction rate and mechanical removal efficiency
Polishing time: Precise control is required based on the amount of material removed and the flatness of the surface

2.5.6 Challenges and improvements of CMP processes

The CMP process faces several challenges, such as polishing uniformity, material selectivity, surface damage, etc. In order to overcome these problems, the industry is constantly making technological improvements:

Optimized slurry formulation: Develop new slurries to improve selectivity and removal rates
Improve polishing pad materials: Improve polishing results with more durable, better-performing polishing pads
Automation and intelligent control: Introduce real-time monitoring and feedback control systems to improve process stability and consistency

In conclusion, the CMP process plays a vital role in semiconductor manufacturing, and with the advancement of technology, its application range and process effect are also increasing.

2.6 Cleaning process

After polishing, the wafer must be thoroughly cleaned to remove any residual particles, contaminants, or chemical residues. A combination of wet and dry cleaning technologies, such as ultrasonic cleaning and plasma cleaning, is commonly used. Ultrasonic cleaning involves immersing the wafer in a cleaning solution and applying ultrasonic vibrations. Plasma cleaning, on the other hand, uses high-energy plasma to remove contaminants from the wafer surface.

The cleaning process in semiconductor processes is a critical step in keeping wafer surfaces clean and removing impurities and contaminants. The cleaning process is used throughout semiconductor manufacturing and includes the following steps and methods:

a. RCA cleaning

RCA-1 Cleaning (Removal of Organic Contaminants): A mixed solution of ammonia, hydrogen peroxide and deionized water is used. This step removes organic contaminants, particles, and metal ions from the wafer surface.
RCA-2 Cleaning (Removal of Metal Ions): A mixed solution of hydrochloric acid, hydrogen peroxide, and deionized water is used. It mainly removes metal ions and some inorganic pollutants that are difficult to remove.
Piranha cleaning uses a mixed solution of sulfuric acid and hydrogen peroxide. Piranha cleaning is very effective at removing organics and surface contaminants and is often used for initial cleaning. c. HF cleaning (hydrofluoric acid cleaning) uses a diluted hydrofluoric acid solution, which is mainly used to remove the oxide layer and some silicon surface contaminants. d. Megasonic cleaning utilizes the cavitation effect of ultrasonic waves, typically in the MHz range, to efficiently remove fine particles and other contaminants and is suitable for sensitive surface cleaning. e. Vapor phase cleaning uses gases or aerosols for cleaning, typical methods include the use of ozone and hydrogen peroxide vapors. This method is suitable for the removal of some specific contaminants and is less damaging to the surface. f. Spray cleaning cleans the wafer surface by spraying deionized water or cleaning liquids at high pressure, often in combination with a rotating device to increase the cleaning effect. g. Cleaning after Chemical Mechanical Polishing (CMP) After the CMP process, a rigorous cleaning is required to remove residues and particles after polishing. A mixed solution of ammonia and hydrogen peroxide is usually used. The final step of deionized water rinsing and drying is usually to rinse with high-purity deionized water and then dry by spin drying or other drying techniques such as Marangoni drying to avoid the formation of water stains and spots.

In conclusion, wafer preparation is a critical step in the semiconductor manufacturing process as it lays the foundation for manufacturing high-quality electronic devices. By carefully controlling the crystal growth, wafer dicing, polishing, and cleaning processes, manufacturers can ensure that their wafers meet the stringent requirements required to produce reliable, high-performance semiconductor devices.

2.7 Doping and ion implantation

。 Doping involves the introduction of impurities or dopants into semiconductor materials that significantly alter their electrical properties. These impurities include trivalent or pentavalent impurities. Common methods for introducing doped atoms are diffusion layer implantation, heating semiconductor materials, and ion implantation. Ion implantation is the most common doping technique and involves bombarding the wafer with an ion beam so that these ions are embedded in the semiconductor material to create the desired n-type or p-type region.

Doping is a critical step in the semiconductor manufacturing process, which involves the intentional introduction of impurities (called dopants) into semiconductor materials to modify their electrical properties. Dopants can create a surplus of free electrons (n-type doping) or a lack of electrons (known as holes, p-type doping), which are essential for the formation of semiconductor devices such as transistors and diodes. Some n-type pentavalent impurities include phosphorus, antimony, and arsenic. Boron, aluminum, gallium, and indium are some of the trivalent p-type impurities. In this section, we will discuss the main techniques of doping, including ion implantation and diffusion, and the importance of precise doping control.

a. Ion implantation

Ion implantation is a widely used doping technique that involves the direct insertion of doped ions into a semiconductor material. The process involves ionizing the required dopings, using an electric field to accelerate the ions and directing them to the wafer surface. High-energy ions penetrate the wafer and are embedded in the crystal lattice, altering the electrical properties of the material. Benefits include:

Precise control of doping concentration and depth
Uniform doping distribution on the wafer surface
Low-temperature processing reduces the risk of wafer damage

However, ion implantation can also cause damage to the crystal lattice and must be repaired through an annealing process.

b. Proliferation

Diffusion is another common doping technique that relies on moving through doped atoms in a semiconductor material at high temperatures. In this process, the wafer is placed in a controlled environment, such as a diffusion furnace, and exposed to a source of doped atoms. The doped atoms diffuse into the wafer, creating a concentration gradient that determines the electrical properties of the material.

Diffusion has several advantages, including the ability to form shallow junctions and doping multiple wafers simultaneously. However, it is often less precise than ion implantation and can result in uneven distribution of dopants on the wafer surface.

c. Precise doping control

Accurate control of the doping process is critical to achieving the desired electrical and performance characteristics of the semiconductor device. Factors such as doping concentration, distribution, and junction depth can significantly affect device characteristics such as threshold voltage, current carrying capacity, and switching speed. As a result, manufacturers must carefully control the doping process to ensure that the device meets stringent performance and reliability requirements.

In conclusion, doping is a fundamental process in semiconductor manufacturing, which makes it possible to create semiconductor devices with tailored electrical properties. By carefully selecting the appropriate doping technology, such as ion implantation or diffusion, and precisely controlling the doping process, manufacturers can produce high-performance semiconductor devices that meet the needs of modern electronic applications.

2.8 Metallization and Interconnection

Metallization and interconnect are important components of semiconductor devices, providing a path to connect the individual elements in an integrated circuit. These connections enable the transmission of electrical signals and power between transistors, resistors, capacitors, and other components on the wafer. In this section, we discuss key aspects of metallization and interconnect, including material selection and scaling and performance-related challenges.

Metallization is the deposition of a metal layer on the surface of a wafer that acts as an electrical connection between parts of a device. After creating a p-type or n-type region, the metallization process ensures an electrical connection between the internal circuits through a conductive material. These metal layers can be deposited by a variety of techniques, such as sputtering or electrochemical deposition (ECD). The metal layers are then patterned and etched to form the desired interconnected structure.

2.8.1 Material Selection

Metallization and interconnect material selection is critical because it directly impacts the performance and reliability of semiconductor devices. Commonly used interconnect materials include aluminum, copper, and tungsten, which have low resistivity, good adhesion, and compatibility with the underlying semiconductor material.

Due to its lower resistivity and higher resistance to electromigration compared to aluminum, copper has become the material of choice for many advanced semiconductor devices. However, it also poses a number of reliability issues. First, copper is susceptible to electromigration at high temperatures, resulting in wire breakage or short circuits. The interface between copper and other materials can cause diffusion problems, resulting in deterioration of component performance. In addition, copper is susceptible to damage in corrosive and oxidizing environments and requires stable passivation layer protection, which adds to the complexity of the manufacturing process. In summary, the reliability issues of copper interconnects are mainly focused on electromigration, interfacial diffusion, and chemical stability.

2.8.2 Scale and Performance Challenges

As the size of semiconductor devices continues to shrink, metallization and interconnect are becoming increasingly critical in terms of device performance and reliability. Reducing the size of the feature results in increased resistance and capacitance, leading to increased power dissipation, signal delay, and potential reliability issues such as electromigration and stress-induced voiding.

However, the reduction in chip size has been a trend in the electronics industry. According to Moore's Law, the number of transistors on a chip doubles every two years. With this shrinkage, semiconductors have now reached a tiny size to handle quantum effects such as tunneling. In this effect, low-energy particles can cross the barrier potential below the threshold voltage.

To address these challenges, researchers are exploring new materials, such as graphene and carbon nanotubes, which may have the potential to improve electrical properties and reduce power consumption. In addition, advances in deposition technology and the use of low dielectric constant materials have helped mitigate the impact of scaling on interconnect performance.

In summary, metallization and interconnect are fundamental components of semiconductor devices, providing the electrical connections that enable the transmission of signals and power between the various elements in an integrated circuit. By carefully selecting the right materials, deposition techniques, and addressing the challenges associated with scaling, manufacturers can continue to push the boundaries of semiconductor device performance and integration.

2.9 Passivation and Encapsulation

Passivation involves applying a thin layer of insulating protection to the surface of the wafer to protect the semiconductor device from environmental factors, reducing the risk of corrosion, contamination, and electrical leakage. Common passivation materials include silicon dioxide (SiO2), silicon nitride (Si3N4), and polyimide, which have good adhesion, low moisture permeability, and compatibility with underlying semiconductor materials.

Chip packaging refers to the technology and process of isolating and protecting the finished semiconductor chip from its external environment, and connecting external circuits through specific interfaces. Chip packaging plays a vital role in semiconductor manufacturing, affecting not only the physical protection and thermal management of the chip, but also its performance, reliability, and operability.

Early package designs were simpler and less tool-intensive, as there was no concept of integration at the time. With the rise of system-in-package (SiP) technology, package designs have become increasingly complex. Today, as concepts such as SiP, advanced packaging, chiplets, and heterogeneous integration gain increasing acceptance in the market, the complexity and flexibility of in-package integration are rapidly increasing, and the requirements for package design are increasing.

2.9.1 Main functions of chip packaging

Protect the chip: Prevent damage to the chip from the external environment (such as humidity, dust, etc.), and provide mechanical and chemical protection
Electrical connection: The internal circuit of the chip is connected to the external circuit to transmit electrical signals through pins, solder balls, or other interfaces
Heat dissipation: Effectively dissipate the heat generated during the operation of the chip to ensure its normal operation
Structural support: Provides the physical support of the chip so that it can be safely mounted on the board

2.9.2 Common types of chip packaging technologies

Through-hole packaging: Early electronics and some industrial applications that require high reliability
Surface Mount Technology (SMT): Modern electronics such as mobile phones, computers, and consumer electronics
芯片级封装（Chip-Scale Package, CSP）：移动设备和高性能计算
Ball Grid Array (BGA): High-performance and high-density integrated circuits, such as microprocessors and graphics processors
堆叠封装（Stacked Package / Package-on-Package, PoP）：移动设备和消费电子产品
System-in-Package (SiP): Complex electronic systems, such as wireless communication modules and sensor systems

g. Future trends: Chip packaging technology is advancing as electronic devices become more miniaturized, high-performance, and low-power. Future trends include:

3D Packaging: Integrate multiple chips in a 3D stack to further improve package density and performance
Advanced encapsulation materials, such as ceramics and novel polymers, to improve heat dissipation and mechanical stability
Higher levels of automation: Increase productivity and consistency, and reduce manufacturing costs

2.9.3 Common advanced packaging processes

System-in-Package (SiP): Multiple chips are packaged in a single package, and the chips are connected to each other through interconnects within the package. This technology enables multi-functional integration without changing the design of individual chips, and is highly flexible
3D Integration: Multiple chips are stacked vertically on top of each other and interconnected using Micro Bumps or Through-Silicon Vias (TSVs). This technology can significantly reduce the package area, improve signal transmission speed, and improve system performance
Wafer-Level Packaging (WLP): It can achieve smaller package size and better performance, and is suitable for applications with high size and power consumption requirements, such as mobile devices
Flip-Chip Technology: Flip the chip so that the connection point on the bottom is in direct contact with the pad on the substrate. This reduces the length of the signal path and improves electrical performance and heat dissipation efficiency
Interposer Technology: Interposer is used to connect different chips together. The interposer can be active (with circuitry) or passive (only as a connecting bridge), and this technology enables efficient interconnection between chips with different technology nodes and materials
Panel-Level Packaging (PLP): A method of encapsulating large panels to improve production efficiency and reduce costs, suitable for mass production of electronic products

In short, advanced packaging processes are constantly evolving, driving the development of electronic products in the direction of higher performance, smaller size, and lower power consumption.

2.10 Testing and Quality Control

Testing and quality control are critical aspects of the semiconductor manufacturing process to ensure that the final product meets performance and reliability specifications. These processes involve a variety of inspection, measurement, and evaluation techniques to identify and correct defects, improve process control, and maintain high manufacturing yields.

Advanced package verification tools include electrical verification and physical verification. Electrical verification covers more than 80 rules to check and verify the entire system for signal integrity, power integrity, and EMI/EMC and other electrical aspects. The physical verification is based on the IC verification tool Calibre, which integrates the Calibre 3D STACK tool specifically for 3D advanced packaging. As the integration and design complexity within packages increases, so do the requirements for verification tools. At the same time, the synergy between package design and chip design is increasing, showing a gradual convergence trend, so the demand for collaborative design is also increasing.

2.10.1 Wafer inspection

Semiconductor wafers are cut from cylindrical silicon crystals or ingots. The flatness of these disc-shaped wafers needs to be controlled within tight tolerances to ensure that the entire wafer surface is suitable for integrated circuit (IC) production. If the diced disc geometry is not up to specification, the wafer may need to be reworked. However, dicing is only the first step in wafer processing, and subsequent steps such as grinding and polishing, thin film deposition, and lithography can add to costs and result in a lot of waste if the wafer fails to meet dimensional specifications.

Semiconductor manufacturers choose capacitance-based inspection and metrology systems to inspect semiconductor wafers. At the front end of the wafer processing process, these systems can measure disc geometry to ensure that these wafers, which are worth thousands of dollars, are suitable for further operations.

Wafer inspection is a critical step in the manufacturing process to identify defects such as grain, scratches, and pattern irregularities that can impact device performance and yield. Optical microscopy serves as a non-destructive and high-throughput detection method for monitoring defects in such systems. Shrinking design rules and increased device aspect ratios have resulted in three-dimensional (3D) architecture defects beyond the traditional optical diffraction depth limit. These structures typically have a height in the micron range and a minimum critical size of around 10 nanometers. For such structures, complex nanophotonic and plasmon effects may be of great value.

These inspection techniques enable early detection and correction of defects, helping to maintain high manufacturing yields and reduce the risk of production failure components.

2.10.2 Electrical testing

Electrical testing is performed at various stages of the semiconductor manufacturing process to evaluate the performance and functionality of the device. Some common electrical testing methods include:

Parametric testing: Measure critical electrical parameters such as voltage, current, and resistance to ensure that the device meets performance specifications
Functional testing: The function of an integrated circuit is tested under specific operating conditions, such as temperature and voltage, to ensure that it is functioning properly
Burn-in testing: Operate devices under accelerated stress conditions, such as high temperatures and voltages, to identify potential reliability issues and eliminate early failures

These test methods help ensure that the final semiconductor device meets its performance and reliability requirements and is suitable for the intended application.

2.10.3 Reliability Assessment

Reliability evaluation is an ongoing process throughout the semiconductor manufacturing process to evaluate and improve the long-term performance and stability of a device. Some common reliability assessment techniques include:

Accelerated Life Testing: Operate devices under extreme stress conditions such as high temperatures, humidity, and voltage to identify potential failure mechanisms and estimate their lifetime
Failure Analysis: Systematically investigate failed devices, identify the root cause of failure, and take corrective action to improve the manufacturing process and device reliability
Statistical Process Control: Monitor and analyze manufacturing data to identify trends, changes, and potential process issues for continuous improvement of the manufacturing process

By implementing a comprehensive test and quality control process, semiconductor manufacturers can ensure that their devices meet the performance and reliability requirements of today's demanding applications, while driving continuous improvements in manufacturing efficiency and yield.

2.11 Conclusion

The semiconductor manufacturing process is a complex and sophisticated sequence of steps that transform raw materials into highly advanced integrated circuits. This process involves a number of critical stages, including wafer preparation, lithography, etching, doping, metallization, passivation, packaging, and testing. As materials, technologies, and devices continue to advance, the semiconductor industry continues to push the boundaries of innovation and scale, making electronic devices smaller, more powerful, and more efficient.

In this article, we take a comprehensive look at the semiconductor manufacturing process, highlighting the key aspects of each stage, the challenges faced by manufacturers, and strategies to address them. By understanding the fundamentals and technologies behind semiconductor manufacturing, we can appreciate the feats of engineering and innovation that have driven rapid progress in the electronics industry and fueled the digital revolution that has transformed our world.

2.12 Frequently Asked Questions About the Semiconductor Manufacturing Process

Q1: Why are silicon wafers used in semiconductor manufacturing?

A: Silicon wafers are the most common substrate materials used in semiconductor manufacturing due to their excellent electrical properties, abundant availability, electrical conductivity, and relatively low cost. Silicon is also highly compatible with various manufacturing processes and can easily alter its electrical properties by doping with impurities.

Question 2: What role does lithography play in semiconductor manufacturing?

A: Photolithography is a critical step in transferring patterns to wafers through masks. It involves the precise transfer of complex patterns to the surface of a wafer, including the layers of transistors, interconnects, and other components, using photosensitive chemicals and ultraviolet light.

Q3: What are the main challenges in reducing the size of semiconductor devices?

A: As semiconductor devices continue to shrink in size, manufacturers face several challenges, including the need for more advanced patterning techniques, thinner layers, and higher density interconnects. In addition, smaller devices often generate more heat, requiring improved thermal management solutions in package design.

epilogue

The semiconductor manufacturing process is a series of highly complex and specialized steps that involve a variety of technologies and processes. From initial crystal growth and wafer preparation to the final packaging of the device, every stage requires attention to detail and precise control to ensure the production of high-quality, reliable electronic components. As technology continues to advance, the semiconductor manufacturing process will continue to evolve, driving the creation of more complex and powerful devices for the electronics industry in the future.

3.1 芯片制造前道工艺（Front-End of Line，FEOL）

Refers to all the steps in the semiconductor manufacturing process, from the silicon wafer to the formation of the basic circuit structure. These steps typically include wafer cleaning, thin film deposition, lithography, etching, ion implantation, diffusion, and oxidation, among others. The significance and importance of the front-end process are mainly reflected in the following aspects:

Formation of the infrastructure: The front-end process is the initial stage of chip manufacturing, and its core task is to form basic circuit components such as transistors. These basic components are the basis for the subsequent circuit function implementation, and if the front-end process is inaccurate or incomplete, it will directly affect the overall performance and reliability of the chip.
Precision and miniaturization: With the development of Moore's Law, chip process nodes continue to shrink, requiring precise control of front-end processes at the nanometer level. For example, the implementation of 7nm, 5nm, and even 3nm process nodes is highly dependent on the refinement and precision of the front-end process. This high-precision manufacturing capability is the key to the advancement of semiconductor technology and the improvement of chip performance.
Material and process innovation: Front-end processes involve a great deal of material science and process innovation. For example, the introduction of new materials and structures, such as high-kappa materials, metal gate technology, and FinFET structures, all need to be realized through front-end processes. These innovations are important means to improve chip performance, reduce power consumption, and increase integration.
Cost and yield management: The complexity and sophistication of the front-end process directly impacts the cost and yield of chip manufacturing. Optimizing the front-end process can not only reduce production costs, but also improve yield and increase production efficiency. Efficient front-end process management is of great significance to the economic benefits of the entire semiconductor industry chain.
Technological competitiveness: Leading front-end process technology is an important part of the core competitiveness of semiconductor enterprises. Mastering the advanced front-end technology can enable enterprises to occupy a dominant position in the fierce market competition and gain more market share and technical discourse.

3.2 芯片后道工艺（Back-end of Line, BEOL）

It is a critical stage in the semiconductor manufacturing process, from wafer fabrication to the formation of the final circuit function. In contrast to the front-end of line (FEOL), which deals with the formation of transistors and other active devices on a wafer, the back-end process mainly involves the construction of metal interconnect layers to ensure that the individual transistors and components can be electrically connected. The following are the detailed steps of the chip back-end process:

介质沉积（Dielectric Deposition）
After the pre-process is completed, the dielectric material, typically silicon dioxide (SiO₂) or other low dielectric constant material, is first deposited on the wafer. These materials act as an insulating layer to prevent electrical signal interference between the metal layers.
光刻（Lithography）
The photolithography process is similar to the pre-process process in that the desired pattern is formed on the dielectric layer through steps such as photoresist coating, exposure, and development. The pattern will be used for subsequent etching steps.
蚀刻（Etching）
Using the pattern formed by photolithography as a mask, the etching process is carried out to remove unwanted dielectric material and form channels or holes. These channels and holes will be used to fill the metal to form an interconnect.
金属沉积（Metal Deposition）
Metals such as copper or aluminium are deposited into etched channels and cavities by means of techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or electroplating. These metal channels are the interconnected wires of the chips that are responsible for transmitting electrical signals.
化学机械抛光（Chemical Mechanical Polishing, CMP）
After the metal has been deposited, it needs to undergo a chemical mechanical polishing (CMP) process. The CMP process polishes excess metal and uneven surfaces to ensure the flatness and thickness uniformity of the metal interconnect layer, ready for the next layer of process.
重复多层互连（Multilayer Interconnection）
Modern integrated circuits often require multi-layer metal interconnects, so the above steps are repeated several times to deposit new dielectric layers, lithography, etching, metal deposition, and CMP until the desired multilayer interconnect structure is formed.
钝化层（Passivation Layer）
Finally, in order to protect the circuit from environmental factors such as humidity and dust, a passivation layer is deposited on the top layer, usually using silicon nitride (Si₃N₄) or other materials.
封装（Packaging）
Once all the circuits and interconnect structures on the wafer are completed, the wafer is cut into individual chips (dies) and then packaged. The packaging process includes mounting the chip on the substrate and connecting the chip to the external circuit through solder balls, bumps, etc., and finally forming a complete integrated circuit product.

The pre-process of chip manufacturing is the foundation and key to semiconductor manufacturing, and its technical level directly determines the performance, cost and market competitiveness of chips. Mastering and continuously improving front-end process technology is an important driving force to promote the development of the semiconductor industry. The back-end process is a crucial part of the chip manufacturing process, and through a series of complex process steps, the interconnection and protection of various components inside the chip are realized. Each step of the process requires highly precise control to ensure the performance and reliability of the final product.

Explain the whole process of chip manufacturing in detail