Verilog Language--Procedures--Always nolatches

网址：https://hdlbits.01xz.net/wiki/Always_nolatches

// synthesis verilog_input_version verilog_2001
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    
    always@(*)
        begin
            case