The Electronic Components Industry Federation (JEDEC) recently officially released the HBM3 high-bandwidth memory standard - JESD238, compared with the HBM2 and HBM2e standards, the performance of HBM3 has once again ushered in a huge improvement. According to the official JEDEC press release, the JESD238 standard specifies developments for the new generation of HBM3 dynamic RAM. HBM3 uses innovative solutions designed to deliver higher bandwidth, lower power consumption, and denser unit capacity to drive experiences in areas such as graphics processing, high-performance computing, and servers.
HBM3 further expands the bandwidth on the HBM2 architecture, doubling the rate per pin to 6.4GB/s for a high bandwidth of 819GB/s. The number of independent channels has also increased from 8 in the HBM2 era to 16, and each channel has two sets of "Pseudo Channels", allowing HBM3 to virtually support up to 32 channels.
In terms of stacking layers, the new standard not only supports 4-Hi, 8-Hi, and 12-Hi through-hole (TSV) stacks, but also prepares for the implementation of 16-Hi solutions. With a capacity density of 8 to 32Gb per layer, it can easily support 4GB (8Gb 4-Hi) to 64GB (32Gb 16-Hi) capacity density, and it is expected that the first generation will be based on the 16Gb storage layer.
To meet the need for reliability, availability, and maintainability (RAS) at the high platform level, HBM3 also supports symbol-based on-chip ECCs, as well as real-time error reporting and transparency. Efficiency performance is further improved by using a low swing (0.4V) signal and a lower operating voltage (1.1V) at the host interface.
Barry Wagner, NVIDIA's technical marketing director and HBM subcommittee, said: "With enhanced performance and reliability attributes, HBM3 will provide strong support for new applications that require huge bandwidth and capacity.
Mark Montierth, vice president and general manager of Micron's High Performance Memory and Networking Business Unit, said that the HBM3 will bring the industry to a higher performance peak, improve reliability and reduce energy consumption. Micron will leverage its advanced experience in memory stacking and packaging to lead the subsequent computing platform market.
Uksong Kang, vice president of dram product planning at SK Hynix, added: "As HPC and AI applications continue to advance, the demand for higher performance and energy efficiency is also accelerating further than ever. With the official release of the JEDEC HBM3 standard, SK Hynix looks forward to providing customers with DRAM products with high performance, optimal energy efficiency and higher stability through the enhanced ECC solution.
John Koeter, vice president of IP and strategic marketing at Synopsys, also said: Synopsys has helped drive the development and adoption of advanced memory interfaces such as HBM3, DDR5, and LPDDR5 in a range of emerging applications. Synopsys' HBM3 IP and authentication solutions have been pioneered by corporate customers. By accelerating the integration of new interfaces with high-performance SoCs, it also facilitates the design and development of multi-chip system-in-packages with high memory bandwidth and energy efficiency.