CISPR5 conduction test of LED drivers
As shown in Figure 14.36, the LED driver board of a BUCK circuit, from the schematic diagram, the green filter input ground and the yellow power ground are separated by the input capacitor, so that the noise current of the high-frequency current loop will pass through the input ceramic capacitor first, but in the actual PCB layout, it can be seen that the input ground and the high-frequency current loop coincide, and the noise can be directly coupled to the input loop.
Figure 14.36 Layout of a BUCK circuit
The actual results are shown in Figure 14.37(a), and the amplitude of the second harmonic is much higher than that of the first harmonic and exceeds the limit. In order to solve this coupling problem, we need to adjust the position of the input ground, which is to disconnect the input ground from the power ground, move it to the right side, and connect it to the input ceramic capacitor through the via. As can be seen, as shown in Figure 14.37(b), the component of the second harmonic decreases by nearly 20 dB.
（a） （b）
Figure 14.37 Comparison before and after layout optimization
However, it can be seen that the noise amplitude near the conduction high frequency of 78~108M is still relatively high, far exceeding the CISPR5 class 5 limit requirements. This part of the noise usually comes mainly from the common-mode current, and the electric field caused by the dv/dt on the board needs to be optimized.
According to the previous analysis, it is possible to suppress noise sources by reducing the SW area and inductor volume. The 10μH inductor and SW copper pour area are relatively large, so while the current capacity is maintained, part of the SW area is cut off and replaced with a smaller inductance inductor. As shown in Figure 14.38, the SW area and inductance are optimized to increase by about 10dB, which basically meets the limit requirements of class 5.
Figure 14.38 Optimization of SW area and inductance and improvement results