Set microgrid news, semiconductor manufacturing process continues to evolve, the requirements for ATE test machine is also getting higher and higher. If the period from 1990 to 2025 is divided into three eras, the demand for ATE test machines for semiconductor chips in each era is different.
Recently, semiconductor test manufacturer TERADYNE (TERADYNE) China deputy general manager of sales Huang Feihong told Jiwei Network that in 1990-2000, the mainstream semiconductor process was 350nm and 130nm, when the SoC chip function is getting stronger and stronger, the chip also integrates analog functions, the transmission rate of the data interface is also increasing, and the original ATE test technology can not cover the needs of analog and high-speed interface testing, so this era can be called the "functional era". The design and development of ATE test machines needed to meet the needs of SoC chips that were becoming increasingly complex at that time.
Between 2000 and 2015, Huang Feihong believes that this is an "era of capital efficiency", as the semiconductor process continues to plummet from 130nm to 14nm, the chip size is getting smaller and smaller, the transistor integration is getting higher and higher, and the challenge is mainly that the test time is very long. Single-station testing in the functional era can no longer meet existing requirements, and the cost of testing is increasing. Therefore, the research and development of ATE testers needs to meet the needs of the same test, and at the same time do 2-station, 4-station, and 8-station tests.
After 2020, the semiconductor process into 5nm, 3nm and below nodes, Huang Feihong said that this is a "complexity era" for THE ATE test machine, the consumer chip life cycle in this era is generally 2-3 years, and even some AI chips and AP chips are iterated year by year, so the ATE test machine is facing different fields and different requirements of complexity adjustment.
On the whole, the challenges posed by semiconductor process exploration to ATE testing mainly come from test time and wafer yield. Huang Feihong told Jiwei Network that the extension of the test time means an increase in the cost of testing. As chips become more complex, wafer's initial yield continues to decline, and the probability of failure increases, so testing is needed to be more accurate.
Faced with different degrees of complex challenges, Teradyne has launched three major test platforms of J750, UltraFLEX and UltraFLEXplus, as well as a unified and compatible software platform IG-XL. In addition, there is an Eagle test platform specifically for power semiconductor chips.
According to Huang Feihong, the J750 mainly provides low-cost solutions for simple chips. UltraFLEX and new member UltraFLEXplus are aimed at relatively more complex chips, with nearly 6,000 UltraFLEX installed around the world and more than 12,000 IG-XL software platforms installed. Over the past six years, IG-XL has been ranked number one software in the global chip industry. Huang Feihong stressed that a good software development platform is especially important for test engineers, which can greatly improve development efficiency.
Specifically, the minimum head of UltraFLEX is HD-12, which means that there are a total of 12 slots that can be used to insert digital boards, and then 24 slots and 36 slots. Huang Feihong pointed out that the original digital board was 256 digital channels, and now it has 512 digital channels, which is also the highest density board in the industry. From Q6 to Q12 to Q24, in fact, according to the different needs of customers, you can flexibly choose the configuration from small to large to meet the test needs of different chips and multiple stations.
UltraFLEXplus' next-generation platform is compact, better integrated than the previous generation of UltraFLEX, and is a fully water-cooled system. Huang Feihong pointed out that on the new platform of UltraFLEXplus, the design of the chip test interface board has been completely revolutionary improved, using Broadside technology, making the application area of the interface board larger, and making the number of PCB layers of the interface board less.
UltraFLEXplus also has four most important advantages, one is the use of unified IG-XL software, the other is the use of PACE architecture, distributed computing control, hash rate decentralization, bringing higher processing efficiency. The third is the Broadside design, in addition to the interface board is larger, all arrangements can achieve complete symmetry. Fourth, from the previous generation of boards to the new generation of boards, whether it is data rate, measurement accuracy, all aspects of the indicators have been greatly improved.
Huang Feihong revealed that the current global installed capacity of UltraFLEXplus has approached 600 units, and in just about a year and a half, this new platform has also been recognized by major customers.