1. Classification of power supply DDR
A、
Mains power VDD and VDDQ
The main power supply requirement is VDDQ=VDD, VDDQ is the power supply to the IO buffer, and VDD is the power supply to the core. However, in general use, VDDQ and VDD are combined into one power supply.
Some chips also have a special VDDL, which supplies power to the DLL, and can also use the same power supply as the VDD.
When designing a power supply, it is necessary to consider whether the voltage and current meet the requirements.
The power-on sequence of the power supply and the power-on time of the power supply, monotonicity, etc.
The power supply voltage requirement is generally within ±5%. The current needs to be calculated according to the number of chips used. Since the current of DDR is generally relatively large, it is the most ideal state to design the PCB if there is a complete power plane laid on the pins, and increase the capacitor energy storage at the power supply inlet, and add a small capacitor filter of 100nF ~ 10nF on each pin.
B、
Refer to the power supply Vref
The reference power supply Vref is required to follow VDDQ, and Vref=VDDQ/2, so it can be provided by the power supply chip, or it can be obtained by resistor divider. Because the general current of Vref is small, in the order of several mA ~ tens of mA, it is recommended to use this method by means of resistor voltage division, which is cost-saving and flexible in layout, and is placed closer to the Vref pin and closely follows the VDDQ voltage. It should be noted that the resistor used for voltage division can be 100Ω~10kΩ, and a resistor with an accuracy of 1% is required. A 10nF capacitor filter is required on each pin of the Vref reference voltage, and a capacitor is also connected in parallel on each voltage divider resistor.
C、
Voltage VVT for matching
VTT is the power supply pulled up by the matching resistor, VTT=VDDQ/2. In the design of DDR, depending on the topology, some designs do not use VTT, such as when the controller has a relatively small number of DDR devices. If VTT is used, the current requirement of VTT is relatively large, so the traces need to be paved with copper skin. In addition, VTT requires that the power supply can both sink and sink current. In general, VTT-generating power chips designed specifically for DDR can be used to meet the requirements.
Moreover, a 10nF~100nF capacitor is generally placed next to each resistor pulled to the VTT, and a uF-level large capacitor is required on the entire VTT circuit for energy storage.
Under normal circumstances, the data line of DDR is a one-drive-one topology, and DDR2 and DDR3 have ODT to match, so there is no need to pull to VTT to match to get better signal quality. If the address and control signal line of DDR2 are multi-loaded, there will be multiple drives in one drive, and there is no ODT inside, and its topology is a T-shaped structure, so it is often necessary to use VTT to match the signal quality.
DDR3 can be routed in a fly-by manner:
A DDR3 design example to analyze the difference between using a high-impedance load trace and using a main line and load trace with the same impedance.
As shown in the figure above, Case1 is designed with an impedance of 50 ohm from the inner controller to each SDRAM. The Case2 is designed with a 40 ohm main line and 60 ohm load line. Simulation tools are used to compare and analyze this.
As can be seen from the above simulated waveforms, Case2 with higher impedance load traces is significantly better than Case1 with the same impedance for branch mains.
Moreover, the load close to the drive end has the greatest effect, and the load away from the drive end has less effect. This is exactly what was analyzed earlier, the distributed capacitance of the load leads to the impedance reduction of the load line part, and if the main line and the load line are designed with the same impedance, it will lead to the occurrence of impedance discontinuity. The load trace is designed with a higher impedance to balance the distributed capacitance introduced by the load, so that the impedance balance of the whole trace can be achieved.
Balancing the load capacitance by increasing the load trace impedance is actually a method that has been often used in daisy-chain designs in the past. DDR3 calls this topology fly-by, which actually has a certain meaning, which is intended to emphasize that the load stub traces are short enough.
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