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DDR memory rate of 6400MT/s and above, an indispensable CKD chip

For the chipset solutions of server memory module RDIMM, Rambus has always had deep technical strength, and can provide a complete set of solutions such as register clock drivers (RCDs), power management chips, serial detection hubs (SPD Hubs), and temperature sensors. And these memory technologies used in the server field are gradually moving to the client field.

CKD came into being

John Eble, Vice President of Product Marketing for Rambus' Memory Interconnect Business Unit, said that in the past, unbuffered DIMMs for desktops and workstations, as well as SO-DIMMs for laptops, did not have logic circuitry to enhance signal integrity. The CPU drives up to four differential clocks directly to the DIMM and the DRAM set on the module. However, the clock comes from a very power-hungry SoC with a lot of power supply noise. The clock signal needs to escape the dense CPU pin area, travel through the motherboard, up to the DIMM socket, and then to the target DRAM on the DIMM.

As speeds get higher, the amount of jitter introduced per bit time increases due to factors such as power supply, inductive jitter crosstalk, and jitter amplification through attenuation. This makes timing budget convergence for synchronous memory interfaces a real challenge.

DDR memory rate of 6400MT/s and above, an indispensable CKD chip

The DDR5 client clock driver, highlighted in blue on the right, is a signal integrity timing enhancement chip (CKD). It restores the clock amplitude and timing fidelity of the individual DRAM on the DIMM. In single-phase lock-loop mode, the CKD receives a single clock from the CPU, recovers the amplitude of the clock, reduces jitter through a phase-locked loop (PLL), and outputs four clean copies. In addition, CKD replaces the need for up to 4 connections from the CPU to the module. This reduces CPU pins and power consumption, and can simplify motherboard wiring.

Since DDR5 modules are dual-channel, there is also a DPL mode in which the two halves of the DIMM can operate independently of each other. There is also a clock phase-locked loop bypass mode for backward compatibility. CKD is essential to maintain clock signal integrity at DDR5 speeds of 6400MT/s and beyond.

Rambus DDR5 CKD的特性

Rambus introduces fully compatible DDR5 client clock driver products that support CUDIMM and CSODIMM speeds up to 7200MT/s for future client generations. These high-bandwidth DIMMs will first be introduced to desktops and laptops to support artificial intelligence, gaming, and content creation.

The image below is a schematic diagram of CSODIMM, which highlights the Rambus CKD and SPD Hub chipset solutions.

DDR memory rate of 6400MT/s and above, an indispensable CKD chip

In single PLL mode, the CKD will receive one clock and two in dual PLL mode, and drive up to four high-precision output clocks depending on DRAM capacity and configuration. CKD can be configured and pulled through its I2C and I3C sideband interfaces, which are buffered by the SPD Hub.

"The main advantage of the Rambus DDR5 CKD is the ultra-low jitter clock. It is the low random jitter and low deterministic jitter that the Rambus solution provides for the DRAM that adds margin to the timing path of the entire system. This is very important to achieve high rates. John Eble analyzed.

Other advantages or values that the device brings include a higher amplitude clock, resulting in greater voltage headroom on the DRAM. CKD can potentially reduce system power consumption and alleviate board routing challenges by eliminating additional clocks in the CPU. In addition, the CKD includes a low-power standby mode, which is essential for laptop systems. There is also a dual-channel phase-locked loop mode to optimize system performance and efficiency.

The chart below compares RCD products to newly released CKD devices. The concept of CUDIMM is largely a scaled-down version of RDIMM, which has been used in servers for many years. The difference is that the RDIMM buffers clock letter, command, and address bus signals, while the CKD in CUDIMM only buffers clock signals.

DDR memory rate of 6400MT/s and above, an indispensable CKD chip

Now, Rambus not only offers chipset solutions for server RDIMMs, but is also working with major DRAM and SOC vendors to introduce new client chipsets for CUDIMMs and CSODIMMs.

Rambus's supply advantage

Mr. Su Lei, General Manager of Rambus Greater China, said that our one-stop solutions come from self-development, and the know how of each component can clearly give suggestions and help to module manufacturers in terms of product design, debugging, etc.

Many of the values we provide to our customers are based on three main points, starting with robust interoperability at the DIMM level. By having a complete chipset, we can ensure that the chips work together seamlessly on the DIMMs from the early design stages through verification. It can provide customers with a high level of verification and peace of mind.

The second advantage is dedicated customer support. Third, maintaining a certification matrix for a robust supply chain can become a considerable burden due to the large number of chip suppliers for memory modules. With a complete chipset solution without the need for a large number of cross-combinations of chip-level configurations. This broad product portfolio makes Rambus a reliable supplier that ensures optimized performance, enhanced robustness, and reduced time to market for customers.

Application Trends

With the increasing popularity of AI large-scale model applications, there is a stronger demand for high memory, low latency, high reliability, and high capacity. For example, there is a very popular game in China recently, which has significantly driven the demand for a series of hardware specifications, including memory. In the future, it is foreseeable that such demand orientation will be normalized, and memory module manufacturers will also further improve the performance of their products with the help of CKD chips, so as to differentiate their module products.

Along with such application requirements, memory will inevitably be updated to products such as CKD, and even changes to the architecture and memory design. Such standards are being developed by JEDEC. Rambus will also be actively involved in the development of these future memory standards and provide cutting-edge memory chips and solutions to the industry.

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