1. MII/GMII(Gigabit Media Independent Interface)
1.1 MII/GMII signal
1.2 MAC <--> PHY
1) GMII:
2) MII:
In 1000BASE-T mode, when the GMII interface is selected, a 125 MHz transmit clock is expected on GTX_CLK.
Although not part of the GMII interface, TX_CLK is still available and can source 25 MHz, 2.5 MHz, or 0 MHz clock
depending on the setting of register 20.6:4; and RX_CLK sources the 125 MHz receive clock. TXD[7:0] and RXD[7:0]
signals are used.
In the 100BASE-TX and 10BASE-T modes, when the MII mode is selected, both TX_CLK and RX_CLK source 25
MHz or 2.5 MHz, respectively. TXD[3:0] and RXD[3:0] signals are used. GTX_CLK and TXD[7:4] signals must be
pulled high or low and must not be left floating. RXD[7:4] pins are driven low
2. Reduced Pin Count GMII (RGMII)
This interface reduces the interconnection between the MAC and the PHY to 12 pins.
transmit and receive clocks operate at 125 MHz, 25 MHz, and 2.5 MHz depending on the speed selected.
When the RGMII mode is selected, transmit control (TX_CTL) is presented on both clock edges of GTX_CLK
(TXC). Receive control (RX_CTL) is presented on both clock edges of RX_CLK (RXC).
This interface can be used to implement 10/100 Mbps Ethernet Media Independent Interface (MII) by reducing the
clock rate to 25 MHz for 100 Mbps operation, and 2.5 MHz for 10 Mbps. The GTX_CLK (TXC) signal is always
generated by the MAC, and the RX_CLK (RXC) signal is generated by the PHY.
3. SGMII
This interface supports 10, 100, and 1000 Mbps modes of operation. The 88E1111 device does not need a TXCLK input as it recovers this clock from input data. This feature has the advantage of reducing pin count, the number of traces on the board, as well as EMI and
noise generation.
On the receive side, 2 modes of operation: one with a receive clock supplied to the MAC, and one without. The
serial interface with clock is selected by setting HWCFG_MODE[3:0] bits to ‘0000’. The serial interface without
clock is selected by setting HWCFG_MODE[3:0] bits to ‘0100’. The receive clock is required for MACs that do not
have clock recovery capability.
SGMII with Receive Reference Clock:
SGMII without Receive Reference Clock:
4. RMII
base on rtl8201