仿真测试的所有文件
modelsim仿真
初始化时序
初始化状态机
去掉多数信号可以看到初始化时序
PRE预充电经过两个周期进入AREF自刷新，自刷新需进行两次，然后进入MREF模式设置，模式设置经过两个周期跳到IDLE
我这里是以100M的时钟给延迟时间，所以各个周期取值都做得比较大
单字节读写，写一个读一个
单字节写命令
先发一个ACT写激活命令经过四个周期进入WR写命令，然后经过四个周期进入PRE预充电命令，预充电延迟两个周期进入IDLE，这里周期取得比较长，可以根据自己需要进行压缩
单字节写状态机
单字节读命令
先发一个ACT命令经过四个周期进入RD读命令，然后经过四个周期进入DATA读取数据，最后发出PRE预充电
单字节读状态机
下图主要是写请求信号，读请求信号以及写数据标志信号和读数据标志信号
注意写数据标志信号和读数据标志信号都提前了一个周期，主要是我们读数据和写数据都是使用非阻塞赋值
自动刷新
自动刷新直接给AREF自动刷新命令，一般取63ns，这里取7个周期
在 modelsim中使用命令行来看状态
写一次，读一次
将data_test模块里的测试长度改为5，然后连续读写5次
下面是所有的仿真文件代码
module sdram_init(
input i_clk,//时钟
input i_rst_n,//复位低有效
input [15:0] current_state,//状态
output reg refresh_req,//自刷新请求
output cnt_200us_flag,//初始化200us完成标志信号
input flag_init_end//初始化完成信号
);
parameter Areflash = 16'b0000000000001000;//自动刷新
reg [14:0] cnt_200us;
reg [9:0] refresh_cnt;
assign cnt_200us_flag = (cnt_200us == 15'd20000)? 1'b1:1'b0;
//计数200us
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
cnt_200us <= 15'd0;
else if(cnt_200us < 15'd20000)//20000
cnt_200us <= cnt_200us + 1'b1;
else
cnt_200us <= cnt_200us;
end
//自动刷新计数
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
refresh_cnt <= 10'd0;
else if(refresh_cnt == 10'd769)
refresh_cnt <= 10'd0;
else if(flag_init_end)
refresh_cnt <= refresh_cnt + 1'b1;
else
refresh_cnt <= refresh_cnt;
end
//自动刷新请求
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
refresh_req <= 1'b0;
else if(current_state == Areflash)
refresh_req <= 1'b0;
else if(refresh_cnt == 10'd769)
refresh_req <= 1'b1;
else
refresh_req <= refresh_req;
end
endmodule
/***************************************************************************************
作者： 李晟
2003-08-27 V0.1 李晟
添加内存模块倒空功能，在外部需要创建事件：sdram_r ,本SDRAM的内容将会按Bank 顺序damp out 至文件
sdram_data.txt 中
×××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××*/
//2004-03-04 陈乃奎 修改原程序中将BANK的数据转存入TXT文件的格式
//2004-03-16 陈乃奎 修改SDRAM 的初始化数据
//2004/04/06 陈乃奎 将SDRAM的操作命令以字符形式表示，以便用MODELSIM监视
//2004/04/19 陈乃奎 修改参数 parameter tAC = 8;
//2010/09/17 罗瑶 修改sdram的大小，数据位宽，dqm宽度;
/****************************************************************************************
*
* File Name: sdram_model.V
* Version: 0.0f
* Date: July 8th, 1999
* Model: BUS Functional
* Simulator: Model Technology (PC version 5.2e PE)
*
* Dependencies: None
*
* Author: Son P. Huynh
* Email: [email protected]
* Phone: (208) 368-3825
* Company: Micron Technology, Inc.
* Model: sdram_model (1Meg x 16 x 4 Banks)
*
* Description: 64Mb SDRAM Verilog model
*
* Limitation: - Doesn't check for 4096 cycle refresh
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
* Copyright ?1998 Micron Semiconductor Products, Inc.
* All rights researved
*
* Rev Author Phone Date Changes
* ---- ---------------------------- ---------- ---------------------------------------
* 0.0f Son Huynh 208-368-3825 07/08/1999 - Fix tWR = 1 Clk + 7.5 ns (Auto)
* Micron Technology Inc. - Fix tWR = 15 ns (Manual)
* - Fix tRP (Autoprecharge to AutoRefresh)
*
* 0.0a Son Huynh 208-368-3825 05/13/1998 - First Release (from 64Mb rev 0.0e)
* Micron Technology Inc.
****************************************************************************************/
`timescale 1ns / 100ps
module sdram_model_plus (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm,Debug);
parameter addr_bits = 13;
parameter data_bits = 16;
parameter col_bits = 9;
parameter mem_sizes = 2*1024-1;//1 Meg
inout [data_bits - 1 : 0] Dq;
input [addr_bits - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [3 : 0] Dqm; //高低各8bit
//added by xzli
input Debug;
reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];//存储器类型数据
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
reg [3 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
reg [addr_bits - 1 : 0] Mode_reg;
reg [data_bits - 1 : 0] Dq_reg, Dq_dqm;
reg [col_bits - 1 : 0] Col_temp, Burst_counter;
reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge
reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command
reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks)
reg Auto_precharge [0 : 3]; // RW AutoPrecharge (Bank)
reg Read_precharge [0 : 3]; // R AutoPrecharge
reg Write_precharge [0 : 3]; // W AutoPrecharge
integer Count_precharge [0 : 3]; // RW AutoPrecharge (Counter)
reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
reg Data_in_enable;
reg Data_out_enable;
reg [1 : 0] Bank, Previous_bank;
reg [addr_bits - 1 : 0] Row;
reg [col_bits - 1 : 0] Col, Col_brst;
// Internal system clock
reg CkeZ, Sys_clk;
reg [21:0] dd;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
// CAS Latency Decode
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
wire Debug; // Debug messages : 1 = On; 0 = Off
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
reg [31:0] mem_d;
event sdram_r,sdram_w,compare;
assign Dq = Dq_reg; // DQ buffer
// Commands Operation
`define ACT 0
`define NOP 1
`define READ 2
`define READ_A 3
`define WRITE 4
`define WRITE_A 5
`define PRECH 6
`define A_REF 7
`define BST 8
`define LMR 9
// // Timing Parameters for -75 (PC133) and CAS Latency = 2
// parameter tAC = 8; //test 6.5
// parameter tHZ = 7.0;
// parameter tOH = 2.7;
// parameter tMRD = 2.0; // 2 Clk Cycles
// parameter tRAS = 44.0;
// parameter tRC = 66.0;
// parameter tRCD = 20.0;
// parameter tRP = 20.0;
// parameter tRRD = 15.0;
// parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
// parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns)
// Timing Parameters for -7 (PC143) and CAS Latency = 3
parameter tAC = 6.5; //test 6.5
parameter tHZ = 5.5;
parameter tOH = 2;
parameter tMRD = 2.0; // 2 Clk Cycles
parameter tRAS = 48.0;
parameter tRC = 70.0;
parameter tRCD = 20.0;
parameter tRP = 20.0;
parameter tRRD = 14.0;
parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns)
// Timing Check variable
integer MRD_chk;
integer WR_counter [0 : 3];
time WR_chk [0 : 3];
time RC_chk, RRD_chk;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
integer test_file;
//*****display the command of the sdram**************************************
parameter Mode_Reg_Set =4'b0000;
parameter Auto_Refresh =4'b0001;
parameter Row_Active =4'b0011;
parameter Pre_Charge =4'b0010;
parameter PreCharge_All =4'b0010;
parameter Write =4'b0100;
parameter Write_Pre =4'b0100;
parameter Read =4'b0101;
parameter Read_Pre =4'b0101;
parameter Burst_Stop =4'b0110;
parameter Nop =4'b0111;
parameter Dsel =4'b1111;
wire [3:0] sdram_control;
reg cke_temp;
reg [8*13:1] sdram_command;
[email protected](posedge Clk)
cke_temp<=Cke;
assign sdram_control={Cs_n,Ras_n,Cas_n,We_n};
[email protected](sdram_control or cke_temp)
begin
case(sdram_control)
Mode_Reg_Set: sdram_command<="Mode_Reg_Set";
Auto_Refresh: sdram_command<="Auto_Refresh";
Row_Active: sdram_command<="Row_Active";
Pre_Charge: sdram_command<="Pre_Charge";
Burst_Stop: sdram_command<="Burst_Stop";
Dsel: sdram_command<="Dsel";
Write: if(cke_temp==1)
sdram_command<="Write";
else
sdram_command<="Write_suspend";
Read: if(cke_temp==1)
sdram_command<="Read";
else
sdram_command<="Read_suspend";
Nop: if(cke_temp==1)
sdram_command<="Nop";
else
sdram_command<="Self_refresh";
default: sdram_command<="Power_down";
endcase
end
//*****************************************************
initial
begin
//test_file=$fopen("test_file.txt");
end
initial
begin
Dq_reg = {data_bits{1'bz}};
{Data_in_enable, Data_out_enable} = 0;
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
{WR_chk[0], WR_chk[1], WR_chk[2], WR_chk[3]} = 0;
{WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0;
{RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0;
{RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0;
{MRD_chk, RC_chk, RRD_chk} = 0;
{RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;
{RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;
{RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;
$timeformat (-9, 0, " ns", 12);
//$readmemh("bank0.txt", Bank0);
//$readmemh("bank1.txt", Bank1);
//$readmemh("bank2.txt", Bank2);
//$readmemh("bank3.txt", Bank3);
/*
for(dd=0;dd<=mem_sizes;dd=dd+1)
begin
Bank0[dd]=dd[data_bits - 1 : 0];
Bank1[dd]=dd[data_bits - 1 : 0]+1;
Bank2[dd]=dd[data_bits - 1 : 0]+2;
Bank3[dd]=dd[data_bits - 1 : 0]+3;
end
*/
initial_sdram(0);
end
task initial_sdram;
input data_sign;
reg [3:0] data_sign;
for(dd=0;dd<=mem_sizes;dd=dd+1)
begin
mem_d = {data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign};
if(data_bits==16)
begin
Bank0[dd]=mem_d[15:0];
Bank1[dd]=mem_d[15:0];
Bank2[dd]=mem_d[15:0];
Bank3[dd]=mem_d[15:0];
end
else if(data_bits==32)
begin
Bank0[dd]=mem_d[31:0];
Bank1[dd]=mem_d[31:0];
Bank2[dd]=mem_d[31:0];
Bank3[dd]=mem_d[31:0];
end
end
endtask
// System clock generator
always
begin
@(posedge Clk)
begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@(negedge Clk)
begin
Sys_clk = 1'b0;
end
end
always @ (posedge Sys_clk) begin
// Internal Commamd Pipelined
Command[0] = Command[1];
Command[1] = Command[2];
Command[2] = Command[3];
Command[3] = `NOP;
Col_addr[0] = Col_addr[1];
Col_addr[1] = Col_addr[2];
Col_addr[2] = Col_addr[3];
Col_addr[3] = {col_bits{1'b0}};
Bank_addr[0] = Bank_addr[1];
Bank_addr[1] = Bank_addr[2];
Bank_addr[2] = Bank_addr[3];
Bank_addr[3] = 2'b0;
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = 2'b0;
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = 1'b0;
// Dqm pipeline for Read
Dqm_reg0 = Dqm_reg1;
Dqm_reg1 = Dqm;
// Read or Write with Auto Precharge Counter
if (Auto_precharge[0] == 1'b1) begin
Count_precharge[0] = Count_precharge[0] + 1;
end
if (Auto_precharge[1] == 1'b1) begin
Count_precharge[1] = Count_precharge[1] + 1;
end
if (Auto_precharge[2] == 1'b1) begin
Count_precharge[2] = Count_precharge[2] + 1;
end
if (Auto_precharge[3] == 1'b1) begin
Count_precharge[3] = Count_precharge[3] + 1;
end
// tMRD Counter
MRD_chk = MRD_chk + 1;
// tWR Counter for Write
WR_counter[0] = WR_counter[0] + 1;
WR_counter[1] = WR_counter[1] + 1;
WR_counter[2] = WR_counter[2] + 1;
WR_counter[3] = WR_counter[3] + 1;
// Auto Refresh
if (Aref_enable == 1'b1) begin
if (Debug) $display ("at time %t AREF : Auto Refresh", $time);
// Auto Refresh to Auto Refresh
if (($time - RC_chk < tRC)&&Debug) begin
$display ("at time %t ERROR: tRC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP)&&Debug) begin
$display ("at time %t ERROR: tRP violation during Auto Refresh", $time);
end
// Precharge to Refresh
if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin
$display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
end
// Record Current tRC time
RC_chk = $time;
end
// Load Mode Register
if (Mode_reg_enable == 1'b1) begin
// Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin
Mode_reg = Addr;
if (Debug) begin
$display ("at time %t LMR : Load Mode Register", $time);
// CAS Latency
if (Addr[6 : 4] == 3'b010)
$display (" CAS Latency = 2");
else if (Addr[6 : 4] == 3'b011)
$display (" CAS Latency = 3");
else
$display (" CAS Latency = Reserved");
// Burst Length
if (Addr[2 : 0] == 3'b000)
$display (" Burst Length = 1");
else if (Addr[2 : 0] == 3'b001)
$display (" Burst Length = 2");
else if (Addr[2 : 0] == 3'b010)
$display (" Burst Length = 4");
else if (Addr[2 : 0] == 3'b011)
$display (" Burst Length = 8");
else if (Addr[3 : 0] == 4'b0111)
$display (" Burst Length = Full");
else
$display (" Burst Length = Reserved");
// Burst Type
if (Addr[3] == 1'b0)
$display (" Burst Type = Sequential");
else if (Addr[3] == 1'b1)
$display (" Burst Type = Interleaved");
else
$display (" Burst Type = Reserved");
// Write Burst Mode
if (Addr[9] == 1'b0)
$display (" Write Burst Mode = Programmed Burst Length");
else if (Addr[9] == 1'b1)
$display (" Write Burst Mode = Single Location Access");
else
$display (" Write Burst Mode = Reserved");
end
end else begin
$display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
end
// REF to LMR
if ($time - RC_chk < tRC) begin
$display ("at time %t ERROR: tRC violation during Load Mode Register", $time);
end
// LMR to LMR
if (MRD_chk < tMRD) begin
$display ("at time %t ERROR: tMRD violation during Load Mode Register", $time);
end
MRD_chk = 0;
end
// Active Block (Latch Bank Address and Row Address)
if (Active_enable == 1'b1) begin
if (Ba == 2'b00 && Pc_b0 == 1'b1) begin
{Act_b0, Pc_b0} = 2'b10;
B0_row_addr = Addr [addr_bits - 1 : 0];
RCD_chk0 = $time;
RAS_chk0 = $time;
if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d", $time, Addr);
// Precharge to Activate Bank 0
if ($time - RP_chk0 < tRP) begin
$display ("at time %t ERROR: tRP violation during Activate bank 0", $time);
end
end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
{Act_b1, Pc_b1} = 2'b10;
B1_row_addr = Addr [addr_bits - 1 : 0];
RCD_chk1 = $time;
RAS_chk1 = $time;
if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d", $time, Addr);
// Precharge to Activate Bank 1
if ($time - RP_chk1 < tRP) begin
$display ("at time %t ERROR: tRP violation during Activate bank 1", $time);
end
end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
{Act_b2, Pc_b2} = 2'b10;
B2_row_addr = Addr [addr_bits - 1 : 0];
RCD_chk2 = $time;
RAS_chk2 = $time;
if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d", $time, Addr);
// Precharge to Activate Bank 2
if ($time - RP_chk2 < tRP) begin
$display ("at time %t ERROR: tRP violation during Activate bank 2", $time);
end
end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
{Act_b3, Pc_b3} = 2'b10;
B3_row_addr = Addr [addr_bits - 1 : 0];
RCD_chk3 = $time;
RAS_chk3 = $time;
if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d", $time, Addr);
// Precharge to Activate Bank 3
if ($time - RP_chk3 < tRP) begin
$display ("at time %t ERROR: tRP violation during Activate bank 3", $time);
end
end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin
$display ("at time %t ERROR: Bank 0 is not Precharged.", $time);
end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin
$display ("at time %t ERROR: Bank 1 is not Precharged.", $time);
end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin
$display ("at time %t ERROR: Bank 2 is not Precharged.", $time);
end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin
$display ("at time %t ERROR: Bank 3 is not Precharged.", $time);
end
// Active Bank A to Active Bank B
if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
end
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
$display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
end
// Auto Refresh to Activate
if (($time - RC_chk < tRC)&&Debug) begin
$display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba);
end
// Record variables for checking violation
RRD_chk = $time;
Previous_bank = Ba;
end
// Precharge Block
if (Prech_enable == 1'b1) begin
if (Addr[10] == 1'b1) begin
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111;
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
RP_chk0 = $time;
RP_chk1 = $time;
RP_chk2 = $time;
RP_chk3 = $time;
if (Debug) $display ("at time %t PRE : Bank = ALL",$time);
// Activate to Precharge all banks
if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) ||
($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin
$display ("at time %t ERROR: tRAS violation during Precharge all bank", $time);
end
// tWR violation check for write
if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) ||
($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin
$display ("at time %t ERROR: tWR violation during Precharge all bank", $time);
end
end else if (Addr[10] == 1'b0) begin
if (Ba == 2'b00) begin
{Pc_b0, Act_b0} = 2'b10;
RP_chk0 = $time;
if (Debug) $display ("at time %t PRE : Bank = 0",$time);
// Activate to Precharge Bank 0
if ($time - RAS_chk0 < tRAS) begin
$display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time);
end
end else if (Ba == 2'b01) begin
{Pc_b1, Act_b1} = 2'b10;
RP_chk1 = $time;
if (Debug) $display ("at time %t PRE : Bank = 1",$time);
// Activate to Precharge Bank 1
if ($time - RAS_chk1 < tRAS) begin
$display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time);
end
end else if (Ba == 2'b10) begin
{Pc_b2, Act_b2} = 2'b10;
RP_chk2 = $time;
if (Debug) $display ("at time %t PRE : Bank = 2",$time);
// Activate to Precharge Bank 2
if ($time - RAS_chk2 < tRAS) begin
$display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time);
end
end else if (Ba == 2'b11) begin
{Pc_b3, Act_b3} = 2'b10;
RP_chk3 = $time;
if (Debug) $display ("at time %t PRE : Bank = 3",$time);
// Activate to Precharge Bank 3
if ($time - RAS_chk3 < tRAS) begin
$display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time);
end
end
// tWR violation check for write
if ($time - WR_chk[Ba] < tWRp) begin
$display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba);
end
end
// Terminate a Write Immediately (if same bank or all banks)
if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin
Data_in_enable = 1'b0;
end
// Precharge Command Pipeline for Read
if (Cas_latency_3 == 1'b1) begin
Command[2] = `PRECH;
Bank_precharge[2] = Ba;
A10_precharge[2] = Addr[10];
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `PRECH;
Bank_precharge[1] = Ba;
A10_precharge[1] = Addr[10];
end
end
// Burst terminate
if (Burst_term == 1'b1) begin
// Terminate a Write Immediately
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Terminate a Read Depend on CAS Latency
if (Cas_latency_3 == 1'b1) begin
Command[2] = `BST;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `BST;
end
if (Debug) $display ("at time %t BST : Burst Terminate",$time);
end
// Read, Write, Column Latch
if (Read_enable == 1'b1 || Write_enable == 1'b1) begin
// Check to see if bank is open (ACT)
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time);
if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time);
if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time);
if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time);
// Read Command
if (Read_enable == 1'b1) begin
// CAS Latency pipeline
if (Cas_latency_3 == 1'b1) begin
if (Addr[10] == 1'b1) begin
Command[2] = `READ_A;
end else begin
Command[2] = `READ;
end
Col_addr[2] = Addr;
Bank_addr[2] = Ba;
end else if (Cas_latency_2 == 1'b1) begin
if (Addr[10] == 1'b1) begin
Command[1] = `READ_A;
end else begin
Command[1] = `READ;
end
Col_addr[1] = Addr;
Bank_addr[1] = Ba;
end
// Read interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Write Command
end else if (Write_enable == 1'b1) begin
if (Addr[10] == 1'b1) begin
Command[0] = `WRITE_A;
end else begin
Command[0] = `WRITE;
end
Col_addr[0] = Addr;
Bank_addr[0] = Ba;
// Write interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Write interrupt Read (terminate Read immediately)
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
// Interrupting a Write with Autoprecharge
if (Auto_precharge[Bank] == 1'b1 && Write_precharge[Bank] == 1'b1) begin
RW_interrupt_write[Bank] = 1'b1;
if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, Bank);
end
// Interrupting a Read with Autoprecharge
if (Auto_precharge[Bank] == 1'b1 && Read_precharge[Bank] == 1'b1) begin
RW_interrupt_read[Bank] = 1'b1;
if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, Bank);
end
// Read or Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
if (Read_enable == 1'b1) begin
Read_precharge[Ba] = 1'b1;
end else if (Write_enable == 1'b1) begin
Write_precharge[Ba] = 1'b1;
end
end
end
// Read with Auto Precharge Calculation
// The device start internal precharge:
// 1. CAS Latency - 1 cycles before last burst
// and 2. Meet minimum tRAS requirement
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 2
((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 1
(Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
(RW_interrupt_read[0] == 1'b1)) begin // Case 3
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Auto_precharge[0] = 1'b0;
Read_precharge[0] = 1'b0;
RW_interrupt_read[0] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
(RW_interrupt_read[1] == 1'b1)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Auto_precharge[1] = 1'b0;
Read_precharge[1] = 1'b0;
RW_interrupt_read[1] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
(RW_interrupt_read[2] == 1'b1)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Auto_precharge[2] = 1'b0;
Read_precharge[2] = 1'b0;
RW_interrupt_read[2] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
(RW_interrupt_read[3] == 1'b1)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Auto_precharge[3] = 1'b0;
Read_precharge[3] = 1'b0;
RW_interrupt_read[3] = 1'b0;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
// Internal Precharge or Bst
if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks
if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
end else if (Command[0] == `BST) begin // BST terminate a read to current bank
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
if (Data_out_enable == 1'b0) begin
Dq_reg <= #tOH {data_bits{1'bz}};
end
// Detect Read or Write command
if (Command[0] == `READ || Command[0] == `READ_A) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
if (Bank_addr[0] == 2'b00) begin
Row = B0_row_addr;
end else if (Bank_addr[0] == 2'b01) begin
Row = B1_row_addr;
end else if (Bank_addr[0] == 2'b10) begin
Row = B2_row_addr;
end else if (Bank_addr[0] == 2'b11) begin
Row = B3_row_addr;
end
Burst_counter = 0;
Data_in_enable = 1'b0;
Data_out_enable = 1'b1;
end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
if (Bank_addr[0] == 2'b00) begin
Row = B0_row_addr;
end else if (Bank_addr[0] == 2'b01) begin
Row = B1_row_addr;
end else if (Bank_addr[0] == 2'b10) begin
Row = B2_row_addr;
end else if (Bank_addr[0] == 2'b11) begin
Row = B3_row_addr;
end
Burst_counter = 0;
Data_in_enable = 1'b1;
Data_out_enable = 1'b0;
end
// DQ buffer (Driver/Receiver)
if (Data_in_enable == 1'b1) begin // Writing Data to Memory
// Array buffer
if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}];
if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}];
if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}];
if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}];
// Dqm operation
if (Dqm[0] == 1'b0) Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
if (Dqm[1] == 1'b0) Dq_dqm [15 : 8] = Dq [15 : 8];
//if (Dqm[2] == 1'b0) Dq_dqm [23 : 16] = Dq [23 : 16];
// if (Dqm[3] == 1'b0) Dq_dqm [31 : 24] = Dq [31 : 24];
// Write to memory
if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0];
if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0];
if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0];
if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0];
if (Bank == 2'b11 && Row==10'h3 && Col[7:4]==4'h4)
$display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
//$fdisplay(test_file,"bank:%h row:%h col:%h write:%h",Bank,Row,Col,Dq_dqm);
// Output result
if (Dqm == 4'b1111) begin
if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end else begin
if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_dqm, Dqm);
// Record tWR time and reset counter
WR_chk [Bank] = $time;
WR_counter [Bank] = 0;
end
// Advance burst counter subroutine
#tHZ Burst;
end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory
//$display("%h , %h, %h",Bank0,Row,Col);
// Array buffer
if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}];
if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}];
if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}];
if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}];
// Dqm operation
if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 : 0] = 8'bz;
if (Dqm_reg0[1] == 1'b1) Dq_dqm [15 : 8] = 8'bz;
if (Dqm_reg0[2] == 1'b1) Dq_dqm [23 : 16] = 8'bz;
if (Dqm_reg0[3] == 1'b1) Dq_dqm [31 : 24] = 8'bz;
// Display result
Dq_reg [data_bits - 1 : 0] = #tAC Dq_dqm [data_bits - 1 : 0];
if (Dqm_reg0 == 4'b1111) begin
if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end else begin
if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0);
end
// Advance burst counter subroutine
Burst;
end
end
// Write with Auto Precharge Calculation
// The device start internal precharge:
// 1. tWR Clock after last burst
// and 2. Meet minimum tRAS requirement
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
always @ (WR_counter[0]) begin
if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 2
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 1
(Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) ||
(RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 2)) begin // Case 3 (stop count when interrupt)
Auto_precharge[0] = 1'b0;
Write_precharge[0] = 1'b0;
RW_interrupt_write[0] = 1'b0;
#tWRa; // Wait for tWR
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
always @ (WR_counter[1]) begin
if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) ||
(RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 2)) begin
Auto_precharge[1] = 1'b0;
Write_precharge[1] = 1'b0;
RW_interrupt_write[1] = 1'b0;
#tWRa; // Wait for tWR
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
always @ (WR_counter[2]) begin
if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) ||
(RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 2)) begin
Auto_precharge[2] = 1'b0;
Write_precharge[2] = 1'b0;
RW_interrupt_write[2] = 1'b0;
#tWRa; // Wait for tWR
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
always @ (WR_counter[3]) begin
if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) ||
(RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 2)) begin
Auto_precharge[3] = 1'b0;
Write_precharge[3] = 1'b0;
RW_interrupt_write[3] = 1'b0;
#tWRa; // Wait for tWR
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
task Burst;
begin
// Advance Burst Counter
Burst_counter = Burst_counter + 1;
// Burst Type
if (Mode_reg[3] == 1'b0) begin // Sequential Burst
Col_temp = Col + 1;
end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
end
// Burst Length
if (Burst_length_2) begin // Burst Length = 2
Col [0] = Col_temp [0];
end else if (Burst_length_4) begin // Burst Length = 4
Col [1 : 0] = Col_temp [1 : 0];
end else if (Burst_length_8) begin // Burst Length = 8
Col [2 : 0] = Col_temp [2 : 0];
end else begin // Burst Length = FULL
Col = Col_temp;
end
// Burst Read Single Write
if (Write_burst_mode == 1'b1) begin
Data_in_enable = 1'b0;
end
// Data Counter
if (Burst_length_1 == 1'b1) begin
if (Burst_counter >= 1) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_2 == 1'b1) begin
if (Burst_counter >= 2) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_4 == 1'b1) begin
if (Burst_counter >= 4) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_8 == 1'b1) begin
if (Burst_counter >= 8) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end
end
endtask
//**********************将SDRAM内的数据直接输出到外部文件*******************************//
/*
integer sdram_data,ind;
[email protected](sdram_r)
begin
sdram_data=$fopen("sdram_data.txt");
$display("Sdram dampout begin ",sdram_data);
// $fdisplay(sdram_data,"Bank0：");
for(ind=0;ind<=mem_sizes;ind=ind+1)
$fdisplay(sdram_data,"%h %b",ind,Bank0[ind]);
// $fdisplay(sdram_data,"Bank1：");
for(ind=0;ind<=mem_sizes;ind=ind+1)
$fdisplay(sdram_data,"%h %b",ind,Bank1[ind]);
// $fdisplay(sdram_data,"Bank2：");
for(ind=0;ind<=mem_sizes;ind=ind+1)
$fdisplay(sdram_data,"%h %b",ind,Bank2[ind]);
// $fdisplay(sdram_data,"Bank3：");
for(ind=0;ind<=mem_sizes;ind=ind+1)
$fdisplay(sdram_data,"%h %b",ind,Bank3[ind]);
$fclose("sdram_data.txt");
//->compare;
end
*/
integer sdram_data,sdram_mem;
reg [23:0] aa,cc;
reg [18:0] bb,ee;
[email protected](sdram_r)
begin
$display("Sdram dampout begin ",$realtime);
sdram_data=$fopen("sdram_data.txt");
for(aa=0;aa<4*(mem_sizes+1);aa=aa+1)
begin
bb=aa[18:0];
if(aa<=mem_sizes)
$fdisplay(sdram_data,"%0d %0h",aa,Bank0[bb]);
else if(aa<=2*mem_sizes+1)
$fdisplay(sdram_data,"%0d %0h",aa,Bank1[bb]);
else if(aa<=3*mem_sizes+2)
$fdisplay(sdram_data,"%0d %0h",aa,Bank2[bb]);
else
$fdisplay(sdram_data,"%0d %0h",aa,Bank3[bb]);
end
$fclose("sdram_data.txt");
sdram_mem=$fopen("sdram_mem.txt");
for(cc=0;cc<4*(mem_sizes+1);cc=cc+1)
begin
ee=cc[18:0];
if(cc<=mem_sizes)
$fdisplay(sdram_mem,"%0h",Bank0[ee]);
else if(cc<=2*mem_sizes+1)
$fdisplay(sdram_mem,"%0h",Bank1[ee]);
else if(cc<=3*mem_sizes+2)
$fdisplay(sdram_mem,"%0h",Bank2[ee]);
else
$fdisplay(sdram_mem,"%0h",Bank3[ee]);
end
$fclose("sdram_mem.txt");
end
// // Timing Parameters for -75 (PC133) and CAS Latency = 2
// specify
// specparam
tAH = 0.8, // Addr, Ba Hold Time
tAS = 1.5, // Addr, Ba Setup Time
tCH = 2.5, // Clock High-Level Width
tCL = 2.5, // Clock Low-Level Width
// tCK = 10.0, // Clock Cycle Time 100mhz
// tCK = 7.5, // Clock Cycle Time 133mhz
tCK = 7, // Clock Cycle Time 143mhz
tDH = 0.8, // Data-in Hold Time
tDS = 1.5, // Data-in Setup Time
tCKH = 0.8, // CKE Hold Time
tCKS = 1.5, // CKE Setup Time
tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
// tAH = 1, // Addr, Ba Hold Time
// tAS = 1.5, // Addr, Ba Setup Time
// tCH = 1, // Clock High-Level Width
// tCL = 3, // Clock Low-Level Width
tCK = 10.0, // Clock Cycle Time 100mhz
tCK = 7.5, // Clock Cycle Time 133mhz
// tCK = 7, // Clock Cycle Time 143mhz
// tDH = 1, // Data-in Hold Time
// tDS = 2, // Data-in Setup Time
// tCKH = 1, // CKE Hold Time
// tCKS = 2, // CKE Setup Time
// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
// $width (posedge Clk, tCH);
// $width (negedge Clk, tCL);
// $period (negedge Clk, tCK);
// $period (posedge Clk, tCK);
// $setuphold(posedge Clk, Cke, tCKS, tCKH);
// $setuphold(posedge Clk, Cs_n, tCMS, tCMH);
// $setuphold(posedge Clk, Cas_n, tCMS, tCMH);
// $setuphold(posedge Clk, Ras_n, tCMS, tCMH);
// $setuphold(posedge Clk, We_n, tCMS, tCMH);
// $setuphold(posedge Clk, Addr, tAS, tAH);
// $setuphold(posedge Clk, Ba, tAS, tAH);
// $setuphold(posedge Clk, Dqm, tCMS, tCMH);
// $setuphold(posedge Dq_chk, Dq, tDS, tDH);
// endspecify
endmodule
module sdram_read_write(
input i_clk,//时钟
input i_rst_n,//复位低有效
input i_rd_trig,//读指示
input i_wr_trig,//写指示
input [15:0] current_state,//状态
output reg rd_req,//读请求
output reg wr_req//写请求
);
parameter Active_wr = 16'b0000000010000000;//写，激活bank，写入行地址
parameter Active_rd = 16'b0000100000000000;//读，激活bank，写入行地址
reg rd_trig_r;//读命令打拍
reg wr_trig_r;//写命令打拍
//i_rd_trig打一拍
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
rd_trig_r <= 1'b0;
else
rd_trig_r <= i_rd_trig;
end
//i_wr_trig打一拍
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
wr_trig_r <= 1'b0;
else
wr_trig_r <= i_wr_trig;
end
//读请求
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
rd_req <= 1'b0;
else if(i_rd_trig && !rd_trig_r)
rd_req <= 1'b1;
else if(current_state == Active_rd)
rd_req <= 1'b0;
else
rd_req <= rd_req;
end
//写请求
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
wr_req <= 1'b0;
else if(i_wr_trig && !wr_trig_r)
wr_req <= 1'b1;
else if(current_state == Active_wr)
wr_req <= 1'b0;
else
wr_req <= wr_req;
end
endmodule
module sdram_rw_test(
input i_clk,//输入时钟100M
input i_rst_n,//复位低有效
inout [15:0] io_sdram_data, //数据总线
output o_sdram_clk, //sdram时钟，100MHz
output [14:0] o_sdram_addr,//输出sdram地址
output o_sdram_cke,//输出sdram时钟片选
output o_sdram_cs,//输出sdram片选
output o_sdram_ras,//输出sdram行有效
output o_sdram_cas,//输出sdram列有效
output o_sdram_we, //输出sdram写有效
output o_sdram_ldqm,//数据掩码
output o_sdram_udqm //数据掩码
);
wire i_rd_trig;
wire i_wr_trig;
wire i_rd_done;
wire i_wr_done;
wire o_data_indi;
wire o_wr_indi;
wire [15:0] wr_data;
reg [15:0] rd_data;
reg [15:0] sdram_wr_data ;//写数据
reg sdram_out_en;
//数据测试模块
data_test data_test_inst(
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.i_wr_indi(o_wr_indi),
.i_data_indi(o_data_indi),
.o_wr_trig(i_wr_trig),
.o_data(wr_data),
.o_wr_done(i_wr_done),
.o_rd_trig(i_rd_trig),
.o_rd_done(i_rd_done)
);
//SDRAM模块
sdram_top sdram_top_inst(
.i_clk(i_clk),//输入时钟100M
.i_rst_n(i_rst_n),//复位低有效
.i_rd_trig(i_rd_trig),//读触发
.i_wr_trig(i_wr_trig),//写触发
.i_rd_done(i_rd_done),//sdram读完成指示信号
.i_wr_done(i_wr_done),//sdram写完成指示信号
.o_wr_indi(o_wr_indi),//写数据有效
.o_data_indi(o_data_indi),//读数据有效
.o_sdram_clk(o_sdram_clk),//sdram时钟，100MHz
.o_sdram_addr(o_sdram_addr),//输出sdram地址
.o_sdram_cke(o_sdram_cke),//输出sdram时钟片选
.o_sdram_cs(o_sdram_cs),//输出sdram片选
.o_sdram_ras(o_sdram_ras),//输出sdram行有效
.o_sdram_cas(o_sdram_cas),//输出sdram列有效
.o_sdram_we(o_sdram_we), //输出sdram写有效
.o_sdram_ldqm(o_sdram_ldqm),//数据掩码
.o_sdram_udqm(o_sdram_udqm)//数据掩码
);
assign io_sdram_data = sdram_out_en ? sdram_wr_data:16'bz ;
//SDRAM输出数据使能
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
sdram_out_en <= 1'd0;
else if(o_wr_indi)
sdram_out_en <= 1'b1;
else
sdram_out_en <= 1'b0;
end
//SDRAM写数据
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
sdram_wr_data <= 16'd0;
else if(o_wr_indi)
sdram_wr_data <= wr_data;
end
//SDRAM读数据
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
rd_data <= 16'd0;
else if(o_data_indi)
rd_data <= io_sdram_data;
end
endmodule
module sdram_top(
input i_clk,//输入时钟100M
input i_rst_n,//复位低有效
input i_rd_trig,//读触发
input i_wr_trig,//写触发
input i_rd_done,//sdram读完成指示信号
input i_wr_done,//sdram写完成指示信号
output o_wr_indi,//写数据有效
output o_data_indi,//读数据有效
output o_sdram_clk,//sdram时钟，100MHz
output [14:0] o_sdram_addr,//输出sdram地址
output o_sdram_cke,//输出sdram时钟片选
output o_sdram_cs,//输出sdram片选
output o_sdram_ras,//输出sdram行有效
output o_sdram_cas,//输出sdram列有效
output o_sdram_we, //输出sdram写有效
output o_sdram_ldqm,//数据掩码
output o_sdram_udqm//数据掩码
);
wire refresh_req;//自刷新请求
wire cnt_200us_flag;//200us标志信号
wire rd_req;//读请求
wire wr_req;//写请求
wire [23:0] o_addr_bus;//地址输出
wire [15:0] current_state;//状态机状态
wire flag_init_end;//初始化完成
assign o_sdram_clk = i_clk;
assign o_sdram_cke = 1'b1 ;
assign o_sdram_ldqm = 1'b0 ;
assign o_sdram_udqm = 1'b0 ;
//初始化和自刷新模块
sdram_init sdram_init_inst(
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.current_state(current_state),
.refresh_req(refresh_req),
.cnt_200us_flag(cnt_200us_flag),
.flag_init_end(flag_init_end)
);
//读写请求模块
sdram_read_write sdram_read_write_inst(
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.i_rd_trig(i_rd_trig),
.i_wr_trig(i_wr_trig),
.current_state(current_state),
.rd_req(rd_req),
.wr_req(wr_req)
);
//控制模块
sdram_control sdram_control_inst(
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.rd_req(rd_req),
.wr_req(wr_req),
.refresh_req(refresh_req),
.cnt_200us_flag(cnt_200us_flag),
.o_wr_indi(o_wr_indi),
.o_data_indi(o_data_indi),
.current_state(current_state),
.flag_init_end(flag_init_end)
);
//命令模块
sdram_cmd sdram_cmd_inst(
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.i_addr_bus(o_addr_bus),
.o_sdram_addr(o_sdram_addr),
.o_sdram_cke(),
.o_sdram_cs(o_sdram_cs),
.o_sdram_ras(o_sdram_ras),
.o_sdram_cas(o_sdram_cas),
.o_sdram_we(o_sdram_we),
.current_state(current_state)
);
//地址产生模块
sdram_address sdram_address_inst(
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.i_rd_done(i_rd_done),
.i_wr_done(i_wr_done),
.i_wr_trig(i_wr_trig),
.i_rd_trig(i_rd_trig),
.o_addr_bus(o_addr_bus)
);
endmodule
`timescale 1ns/1ps
module sdram_top_tb ;
reg i_clk ;//系统时钟
reg i_rst_n ;//reset, 低电平有效
wire [14:0] o_sdram_addr;
wire [15:0] io_sdram_data;
wire o_sdram_clk;
wire o_sdram_cke;
wire o_sdram_cs;
wire o_sdram_ras;
wire o_sdram_cas;
wire o_sdram_we;
wire o_sdram_ldqm;
wire o_sdram_udqm;
initial begin
i_clk = 1'b0 ;
i_rst_n = 1'b0 ;
#200
i_rst_n = 1'b1 ;
end
always #10 i_clk = ~i_clk ;
sdram_rw_test sdram_rw_test_inst(
.i_clk ( i_clk),
.i_rst_n ( i_rst_n),
.io_sdram_data (io_sdram_data), //数据总线
.o_sdram_clk (o_sdram_clk), //sdram时钟，100MHz
.o_sdram_addr (o_sdram_addr), //地址总线
.o_sdram_cke (o_sdram_cke), //控制信号
.o_sdram_cs (o_sdram_cs),
.o_sdram_ras (o_sdram_ras),
.o_sdram_cas (o_sdram_cas),
.o_sdram_we (o_sdram_we),
.o_sdram_ldqm (o_sdram_ldqm),
.o_sdram_udqm (o_sdram_udqm)
);
sdram_model_plus sdram_model_plus_inst(
.Dq(io_sdram_data),
.Addr(o_sdram_addr),
.Ba({o_sdram_addr[14],o_sdram_addr[13]}),
.Clk(o_sdram_clk),
.Cke(o_sdram_cke),
.Cs_n(o_sdram_cs),
.Ras_n(o_sdram_ras),
.Cas_n(o_sdram_cas),
.We_n(o_sdram_we),
.Dqm({2'b00,o_sdram_ldqm,o_sdram_udqm}),
.Debug(1'b1)
);
endmodule
module data_test(
input i_clk ,
input i_rst_n ,
input i_wr_indi ,
input i_data_indi ,
output reg o_wr_trig ,
output [15:0] o_data ,
output reg o_wr_done ,
output reg o_rd_trig ,
output reg o_rd_done
);
parameter test_lengt = 16'd5;//数据测试长度
reg wr_indi_r;
reg data_indi_r;
reg [15:0] init_cnt;
reg [15:0] wr_count;
reg [15:0] rd_count;
reg [4:0] count;
wire flag_p1;
wire flag_p2;
assign flag_p1 = !i_wr_indi && wr_indi_r;//下降沿检测
assign flag_p2 = !i_data_indi && data_indi_r;//下降沿检测
//读有效信号打一拍
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
wr_indi_r <= 1'b0;
else
wr_indi_r <= i_wr_indi;
end
//写有效信号打一拍
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
data_indi_r <= 1'b0;
else
data_indi_r <= i_data_indi;
end
//初始化计数
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
init_cnt <= 16'd0;
else if(init_cnt == 16'd25500)
init_cnt <= init_cnt;
else
init_cnt <= init_cnt + 1'b1;
end
//读写间隔计数
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
count <= 5'd0;
else if(count == 5'd20)
count <= 5'd0;
else
count <= count + 1'b1;
end
//写数据计数
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
wr_count <= 16'd0;
else if(flag_p1)
wr_count <= wr_count + 1'b1;
else
wr_count <= wr_count;
end
//读数据计数
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
rd_count <= 16'd0;
else if(flag_p2)
rd_count <= rd_count + 1'b1;
else
rd_count <= rd_count;
end
//输出写命令
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
o_wr_trig <= 1'd0;
else if(o_wr_done)
o_wr_trig <= 1'd0;
else if(init_cnt == 16'd25500 && count == 5'd20)
o_wr_trig <= 1'b1;
else
o_wr_trig <= 1'd0;
end
//输出读命令
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
o_rd_trig <= 1'd0;
else if(o_rd_done)
o_rd_trig <= 1'd0;
else if(init_cnt == 16'd25500 && count == 5'd20 && o_wr_done)
o_rd_trig <= 1'b1;
else
o_rd_trig <= 1'd0;
end
//输出写完成信号
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
o_wr_done <= 1'd0;
else if(wr_count == (test_lengt - 1'b1) && flag_p1)
o_wr_done <= 1'b1;
else
o_wr_done <= o_wr_done;
end
//输出读完成信号
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
o_rd_done <= 1'd0;
else if(rd_count == (test_lengt - 1'b1) && flag_p2)
o_rd_done <= 1'b1;
else
o_rd_done <= o_rd_done;
end
assign o_data = (i_wr_indi)? wr_count:16'bz;
endmodule
module sdram_address(
input i_clk,//时钟
input i_rst_n,//复位低有效
input i_rd_done,//读完成信号
input i_wr_done,//写完成信号
input i_wr_trig,//写触发
input i_rd_trig,//读触发
output reg [23:0] o_addr_bus//输出地址
);
reg [2:0] crt_state;
reg [2:0] next_state;
parameter Idle = 3'b001 ;
parameter Wr = 3'b010 ;
parameter Rd = 3'b100 ;
reg rd_sdram_done ;
reg wr_sdram_done ;
reg wr_trig_r ;
reg rd_trig_r ;
reg [23:0] addr_bus_low ;//产生sdram地址
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
crt_state <= Idle ;
else
crt_state <= next_state;
end
//sdram读写完成指示信号
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)begin
rd_sdram_done <= 1'b0;
wr_sdram_done <= 1'b0;
end
else begin
rd_sdram_done <= i_rd_done;
wr_sdram_done <= i_wr_done;
end
end
//写触发信号打一拍
always @(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
wr_trig_r <= 1'b0 ;
else
wr_trig_r <= i_wr_trig ;
end
//读触发信号打一拍
always @(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
rd_trig_r <= 1'b0 ;
else
rd_trig_r <= i_rd_trig ;
end
//sdram地址计数
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
addr_bus_low <= 16'b0 ;
else if(crt_state[0])
addr_bus_low <= 16'b0 ;
else if((crt_state[1]&&(!wr_trig_r&& i_wr_trig))||(crt_state[2]&&(!rd_trig_r && i_rd_trig ))) //
addr_bus_low <= addr_bus_low +1'b1;
else
addr_bus_low <= addr_bus_low ;
end
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
o_addr_bus <= 16'b0;
else
o_addr_bus <= addr_bus_low;
end
///=========================================================================
[email protected]( *)
case(crt_state)
Idle: if(!wr_trig_r&& i_wr_trig )//写触发到来
next_state = Wr ;
else if(!rd_trig_r&&i_rd_trig )//读触发到来
next_state = Rd ;
else
next_state = crt_state ;
Wr: if(!wr_sdram_done&&i_wr_done)//写完指示到来
next_state = Idle ;
else
next_state = crt_state ;
Rd: if(!rd_sdram_done&&i_rd_done)//读完指示到来
next_state = Idle ;
else
next_state = crt_state ;
default :next_state = Idle ;
endcase
endmodule
module sdram_cmd(
input i_clk,//系统时钟
input i_rst_n,//复位低有效
input [23:0] i_addr_bus,//输入地址
input [15:0] current_state,
output wire [14:0] o_sdram_addr,//输出sdram地址
output wire o_sdram_cke,//输出sdram时钟片选
output wire o_sdram_cs,//输出sdram片选
output wire o_sdram_ras,//输出sdram行有效
output wire o_sdram_cas,//输出sdram列有效
output wire o_sdram_we //输出sdram写有效
);
parameter Idle = 16'b0000000000000001;//初始状态
parameter Precharge = 16'b0000000000000010;//预充电
parameter Pre_nop = 16'b0000000000000100;//预充电延时
parameter Areflash = 16'b0000000000001000;//自动刷新
parameter Are_nop = 16'b0000000000010000;//自动刷新延时
parameter Set_mode = 16'b0000000000100000;//模式设置
parameter Set_nop = 16'b0000000001000000;//模式设置延时
parameter Active_wr = 16'b0000000010000000;//写，激活bank，写入行地址
parameter Act_wr_nop = 16'b0000000100000000;//写，激活延时
parameter Write = 16'b0000001000000000;//写人列地址，发出写命令
parameter Wr_nop = 16'b0000010000000000;//写入延时
parameter Active_rd = 16'b0000100000000000;//读，激活bank，写入行地址
parameter Act_rd_nop = 16'b0001000000000000;//读，激活延时
parameter Read = 16'b0010000000000000;//写入列地址，发出写命令
parameter Wait_nop = 16'b0100000000000000;//等待
parameter Data_indi = 16'b1000000000000000;//fpga读数据
reg [14:0] sdram_addr ;
reg [4:0] sdram_cmd ;
wire [12:0] row_addr;
wire [8:0] col_addr;
wire [1:0] bank_addr;
assign col_addr = i_addr_bus[8:0]; // i_addr_bus[8:0] 列地址
assign row_addr = i_addr_bus[21: 9]; //i_addr_bus[21:9] 行地址
assign bank_addr = i_addr_bus[23:22]; // i_addr_bus[23:22] bank地址
[email protected]( *)
case(current_state)
Data_indi,Idle,
Pre_nop,Are_nop,
Set_nop,Act_wr_nop,
Wr_nop,Act_rd_nop,
Wait_nop: sdram_cmd = 5'b10111 ; //上电
Precharge: sdram_cmd = 5'b10010 ; //对bank预充电
Areflash: sdram_cmd = 5'b10001 ; //自刷新
Set_mode: sdram_cmd = 5'b10000 ; //模式设置
Active_rd,Active_wr: sdram_cmd = 5'b10011 ; //激活bank
Write: sdram_cmd = 5'b10100 ; //写操作的列地址
Read: sdram_cmd = 5'b10101 ; //读操作的列地址
default: sdram_cmd = 5'b10111 ;
endcase
assign {o_sdram_cke,o_sdram_cs,o_sdram_ras,o_sdram_cas,o_sdram_we} = sdram_cmd;
[email protected]( *)
case(current_state)
Precharge: sdram_addr =15'b000_0100_0000_0000 ; //A10=1对bank充电
Set_mode: sdram_addr =15'b000_0000_0011_0000 ; //模式设置
//burst type interleave ，cas延时3， write_mode 为0
Active_rd,Active_wr: sdram_addr = {bank_addr,row_addr} ; //激活bank，bank、行地址
Write,Read: sdram_addr = {bank_addr,4'b0,col_addr} ; //列地址
default: sdram_addr = 15'b0 ;
endcase
assign o_sdram_addr = sdram_addr;
endmodule
module sdram_control(
input i_clk,//时钟
input i_rst_n,//复位低有效
input rd_req,//读请求
input wr_req,//写请求
input refresh_req,//自动刷新请求
input cnt_200us_flag,//初始化200us标志信号
output o_wr_indi,//写数据有效
output o_data_indi,//读出数据有效
output reg [15:0] current_state,//状态输出
output reg flag_init_end//初始化完成信号
);
parameter Idle = 16'b0000000000000001;//初始状态
parameter Precharge = 16'b0000000000000010;//预充电
parameter Pre_nop = 16'b0000000000000100;//预充电延时
parameter Areflash = 16'b0000000000001000;//自动刷新
parameter Are_nop = 16'b0000000000010000;//自动刷新延时
parameter Set_mode = 16'b0000000000100000;//模式设置
parameter Set_nop = 16'b0000000001000000;//模式设置延时
parameter Active_wr = 16'b0000000010000000;//写，激活bank，写入行地址
parameter Act_wr_nop = 16'b0000000100000000;//写，激活延时
parameter Write = 16'b0000001000000000;//写人列地址，发出写命令
parameter Wr_nop = 16'b0000010000000000;//写入延时
parameter Active_rd = 16'b0000100000000000;//读，激活bank，写入行地址
parameter Act_rd_nop = 16'b0001000000000000;//读，激活延时
parameter Read = 16'b0010000000000000;//写入列地址，发出写命令
parameter Wait_nop = 16'b0100000000000000;//等待
parameter Data_indi = 16'b1000000000000000;//fpga读数据
//控制状态
reg [15:0] next_state ;
reg [31:0] state_shift ;//状态转换控制，控制一个命令的周期
reg [24:0] initial_cnt;//初始化计数
reg [7:0] refresh_state ;//自刷新周期
/*********************************************/
//状态转换为ASCII码便于仿真，无实际功能
reg [127:0] monitor_state;
[email protected](*)
case(current_state)
Idle :monitor_state = "Idle";
Precharge :monitor_state = "PRE";
Pre_nop :monitor_state = "NOP";
Areflash :monitor_state = "AREF";
Are_nop :monitor_state = "NOP";
Set_mode :monitor_state = "MRSET";
Set_nop :monitor_state = "NOP";
Active_wr :monitor_state = "ACT";
Act_wr_nop:monitor_state = "NOP";
Write :monitor_state = "WR";
Wr_nop :monitor_state = "NOP";
Active_rd :monitor_state = "ACT";
Act_rd_nop:monitor_state = "NOP";
Read :monitor_state = "RD";
Wait_nop :monitor_state = "NOP";
Data_indi :monitor_state = "DATA";
endcase
/********************************************/
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
current_state <= Idle;
else
current_state <= next_state;
end
//初始化周期控制
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
initial_cnt <= 25'h1;
else if(initial_cnt[23])
initial_cnt <= initial_cnt;
else if(cnt_200us_flag)
initial_cnt <= initial_cnt<<1;
else
initial_cnt <= initial_cnt;
end
//初始化完成标志信号
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
flag_init_end <= 1'b0;
else if(initial_cnt[23])
flag_init_end <= 1'b1;
else
flag_init_end <= flag_init_end;
end
//状态机周期控制
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
state_shift <= 32'h1;
else if(current_state[0])
state_shift <= 32'h1;
else if(initial_cnt[23] && current_state != Idle && current_state != Areflash && current_state != Are_nop)
state_shift <= state_shift<<1 ;
end
//自动刷新周期控制
[email protected](posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
refresh_state <= 8'h1 ;
else if(current_state[0])
refresh_state <= 8'h1 ;
else if(current_state == Areflash || current_state == Are_nop)
refresh_state <= refresh_state<<1;
end
//写数据有效标志信号,提前一个周期
assign o_wr_indi = (current_state==Act_wr_nop && state_shift[4])? 1'b1:1'b0;
//读数据有效标志信号,提前一个周期
assign o_data_indi =(current_state==Wait_nop && state_shift[8])? 1'b1:1'b0;
[email protected]( *)
case(current_state)
Idle : if(initial_cnt[1]) //上电，跳到预充电状态
next_state = Precharge ;
else if(refresh_req)//定时刷新
next_state = Areflash ;
else if(wr_req)//
next_state = Active_wr ;
else if(rd_req)
next_state = Active_rd ;
else
next_state = current_state ;
Precharge: if(initial_cnt[2]) //预充电
next_state = Pre_nop ;
else if(state_shift[10])
next_state = Pre_nop ;
else
next_state = current_state ;
Pre_nop: if(initial_cnt[4])
next_state = Areflash ;
else if(state_shift[12])
next_state = Idle ;
else
next_state = current_state ;
Areflash: if(initial_cnt[5]) //自刷新
next_state = Are_nop ;
else if(initial_cnt[13])
next_state = Are_nop ;
else if(refresh_state[0])
next_state = Are_nop ;
else
next_state = current_state ;
Are_nop : if(initial_cnt[12])
next_state = Areflash ;
else if(initial_cnt[20])
next_state = Set_mode ;
else if(refresh_state[7])
next_state = Idle ;
else
next_state = current_state ;
Set_mode : if(initial_cnt[21]) //模式设置
next_state = Set_nop ;
else
next_state = current_state ;
Set_nop : if(initial_cnt[23])
next_state = Idle ;
else
next_state = current_state ;
Active_wr : if(state_shift[0]) //写激活
next_state = Act_wr_nop ;
else
next_state = current_state ;
Act_wr_nop: if(state_shift[4])
next_state = Write ;
else
next_state = current_state ;
Write : if(state_shift[5]) //写命令
next_state = Wr_nop ;
else
next_state = current_state ;
Wr_nop : if(state_shift[9])
next_state = Precharge ;
else
next_state = current_state ;
Active_rd : if(state_shift[0]) //读激活
next_state = Act_rd_nop ;
else
next_state = current_state ;
Act_rd_nop: if(state_shift[4])
next_state = Read ;
else
next_state = current_state ;
Read : if(state_shift[5]) //读命令
next_state = Wait_nop ;
else
next_state = current_state ;
Wait_nop : if(state_shift[8])
next_state = Data_indi ;
else
next_state = current_state ;
Data_indi: if(state_shift[9])
next_state = Precharge ;
else
next_state = current_state ;
default: next_state = Idle ;
endcase
endmodule